Accumulators - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
5.1 Data Arithmetic Unit

5.1.4 Accumulators

The accumulators a0 and a1 are 36 bits wide. The contents of either the high half of the accumulator (bits 31—16)
or the low half of the accumulator (bits 15—0) can be transferred to the 16-bit data bus.
Use of the 36-bit accumulators:

aS means high half; aSl means low half (aS[l] means either aS or aSl can be selected; S is replaced by 0 or 1).

For all types of instructions, writing aSl does not affect aS (high). For data move instructions only, writing
aS (high) either does not affect aSl or clears aSl corresponding to the state of auc[5:4] as follows:
— If auc[5] = 0, a1l is cleared with a write to a1
— If auc[5] = 1, a1l is not cleared with a write to a1
— If auc[4] = 0, a0l is cleared with a write to a0
— If auc[4] = 1, a0l is not cleared with a write to a0

For all types of instructions if aS is written (bits 31—16), bit 31 is sign-extended to bits 35—32.

Bits 35—32 are calculated for addition and subtraction operations to the accumulators (including the special
function operations: incrementing, two's complement, and rounding), thereby indicating overflows.

Access to the guard bits (35—32) for reading and writing is provided by the psw register.

For data move instructions and for the transfer field of multiply ALU instructions (see
the 36-bit value in an accumulator can be transferred to another register or to a memory location. In these
cases, saturation on overflow can be enabled or disabled as follows:
— If auc[3] = 0, saturation is enabled for a1
— If auc[3] = 1, saturation is disabled for a1
— If auc[2] = 0, saturation is enabled for a0
— If auc[2] = 1, saturation is disabled for a0

The overflow condition exists if the value in the 36-bit accumulator is too large to be represented as a 32-bit num-
ber, i.e., if bits 35—31 are not all zeros or all ones. If saturation is enabled and overflow occurs, the value that is
transferred is the most positive or most negative number described below. The value in the accumulator remains
unchanged.
Transfers of data from the p register to the accumulators have four options for scaling that are selected by encoding
the ALIGN field of the auc register (see
To write the contents of a 32-bit register (y, a0, or a1) to RAM requires two instructions: write the data in the high
half of the register to RAM and write the data in the low half of the register to RAM. The order of the two writes to
memory is left to the programmer. To read the contents of RAM to a 32-bit register also requires two instructions.
If clearing the low half of the destination's 32-bit register is enabled by using the CLR field in the auc register, the
read data in RAM to a 32-bit register must be done in the following order: load data to the high half of the register
and then load data to the low half of the register. This order is necessary because a load to the low half of a regis-
ter does not change the data in the high half, but a load to the high half of a register clears the data in the low half.
If clearing of the low half of the register is disabled, the two register loads can be performed in either order.
A write to the high half of the p register has no effect on the low half, there is no option that allows clearing the low
half when the high half is written.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
Most Positive Number: 2
Most Negative Number: –2
Section 3.3, Arithmetic and
DRAFT COPY
31
– 1 = 0x7FFF FFFF
31
= 0x8000 0000
Precision).
Core Architecture
Section 4.5, Instruction Set),
5-3