Table 2-4. Single-Cycle Instruction Internal Pipeline - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Hardware Architecture
2.1 Device Architecture Overview
2.1.5 Internal Instruction Pipeline (continued)
Table 2-4 illustrates the internal pipeline for single-cycle instructions such as a multiply-ALU instruction involving a
read from RAM to the DAU. Each instruction cycle corresponds to one cycle of the non-wait-stated CKO. The
instructions shown on the XAB bus will appear one phase (1⁄2 an instruction cycle) later on the external memory
address bus.

Table 2-4. Single-Cycle Instruction Internal Pipeline

Instruction CKO
Cycle Level
1 1
1 0
2 1
2 0
3 1
3 0
4 1
4 0
The following describes the actions associated with each of the steps shown in bold in
Instruction CKO
Level
Cycle
1 1
1 0
2 1
2 0
3 1
3 0
4 1
4 0
2-14
(continued)
XAB XDB
xaddr instr
1 0
— —
xaddr instr
2 1
— —
xaddr instr
3 2
— —
xaddr instr
4 3
— —
The program counter (PC) places xaddr
(X space memory).
The program memory is accessed.
The program memory responds by placing instr
The AAU decoder decodes the instruction and sets up the YAAU to address the RAM.
The YAAU places yaddr
decodes instr .
1
The decoders direct a RAM read of data
The RAM is being accessed.
The RAM places the data on the YDB, and it is loaded into the DAU.
DRAFT COPY
AAU
DECODE DECODE
—
instr
0
—
instr
1
—
instr
2
—
instr
3
Process Description
on the address bus XAB to program memory
1
1
on the address bus YAB to the RAM. Also, the DAU decoder
1
to the DAU.
1
Information Manual
DAU YAB
instr yaddr
–1 –1
instr —
–1
instr yaddr
0 0
instr —
0
instr yaddr
1 1
instr —
1
instr yaddr
2 2
instr —
2
Table 2-4.
on the instruction data bus (XDB).
Lucent Technologies Inc.
April 1998
YDB
—
data
–2
—
data
–1
—
data
0
—
data
1