General Description; Architecture - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Introduction April 1998

1.1 General Description

1.1.1 Architecture

The DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 are made up of the DSP1600 core pro-
cessor, a dual-port RAM, ROM, and several peripheral blocks. The core contains the data arithmetic unit, the
memory addressing units, the cache, and the control section.
The data arithmetic unit (DAU) is the main computational execution unit of the processor. It supports a 16-bit x
16-bit multiply, a 36-bit ALU operation, and two 16-bit data fetches from memory in a single instruction cycle. The
DAU is made up of two input data registers, the multiplier, two accumulators, the ALU, and various control registers.
The product from the multiplier can be accumulated in one of the two 36-bit accumulators. The data in these accu-
mulators can be directly loaded from or stored to memory in 16-bit words. The ALU supports a full set of arithmetic
and logic operations on either 16- or 32-bit data. Because a standard set of ALU conditions can be tested to per-
form conditional branches and subroutine calls, the processor functions as a powerful 16-bit or 32-bit microproces-
sor for logical and control applications.
A bit manipulation unit (BMU) is provided to accelerate signal coding algorithms. It performs full 36-bit barrel shift-
ing, normalization, and bit field extraction or insertion of data in the accumulators. Two alternate accumulators pro-
vide storage for 36-bit data.
An on-chip cache memory can selectively store repetitive operations like those found in an FIR or IIR filter section.
The code in the cache can repeat up to 127 times with no looping overhead. In addition, operations in the cache
that require an X-memory data access (for example, reading fixed coefficients) execute at twice the normal rate.
The cache greatly reduces the need for writing in-line repetitive code and, therefore, reduces program memory size
requirements. In addition, power consumption is reduced because use of the cache eliminates a memory access
for instruction fetches.
Two addressing units support high-speed, register-indirect memory addressing with postincrementing of the regis-
ter. Four address pointer registers can be used for either read or write addresses to the RAM. One address regis-
ter is dedicated to the instruction/coefficient memory space for table look-up. Direct data addressing is supported
for 16 key registers. A unique compound addressing mode that swaps data between a register and memory in only
two instruction cycles is available. Immediate addressing can be done by using a 9-bit address in a one-cycle
instruction or a 16-bit address in a two-cycle instruction.
The DSP1611/17/18/27/28/29 on-chip memory includes both ROM and dual-port RAM. The RAM has separate
ports to the instruction/coefficient bus and the data bus, and it can write either bus. A program can be downloaded
from slow off-chip memory into the RAM and then executed at full-speed without wait-states. The RAM can also be
downloaded through the JTAG interface for full-speed, remote, in-circuit emulation or for self-test.
The external memory interface (EMI) connects either the instruction/coefficient buses or the data buses to the
external memory buses. The bit input/output (BIO) unit has eight pins that can be individually selected as inputs or
outputs. The timer provides programmable periodic interrupts. The JTAG interface is a four-wire standard test port
defined by IEEE P1149.1. On-chip hardware development system (HDS) circuitry performs instruction break-
pointing and branch tracing in support of full-speed, in-circuit emulation with only the low-speed serial JTAG inter-
face required off-chip.
The DSP1611/17/18/27/28/29 have both a parallel I/O port (PIO or PHIF) and two serial I/O ports (SIO). The serial
I/O units are double-buffered and easily interface to other DSP1600 family devices, commercially available codecs,
and time-division multiplexed (TDM) channels with few, if any, additional components. Both ports connect as many
as eight DSPs in multiprocessor operation. The parallel I/O unit is capable of interfacing to an 8-bit bus containing
other DSP1600 family devices, microprocessors, microprocessor peripherals, or other I/O devices.
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