Loopback Control; Power Management - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Serial I/O
7.2 User-Controlled Features
(continued)

7.2.2 Loopback Control

For testing purposes, the DO output can be looped back to the DI input by encoding the ioc register. Bit 9 of ioc is
the SIOLBC field. If set, the loopback is in effect. To exercise the loopback, the SIO clocks (ICK and OCK) should
be in the active mode, 16-bit length, or the user should drive ICK and OCK with a clock as in passive mode. Simi-
larly, ILD and OLD can be in active mode or can be tied together and driven from an external frame clock in passive
mode. A typical test program sequence would be to initialize the control registers, write a word to sdx (the output
buffer), poll to see when the output buffer empties, poll to see if the input buffer is full, and read from sdx. The
input buffer full flag or the output buffer empty flag can also be used to check for the data transfer.
Note: sdx has separate input and output buffers.
During loopback in active mode, the output pins for DO, ICK, OCK, OLD, ILD, SYNC, SADD, and DOEN are
3-stated.

7.2.3 Power Management

Bit 7 of the powerc register (SIO1DIS) is a powerdown signal to the SIO1 I/O unit. It disables the clock input to the
unit eliminating any sleep power associated with the SIO1. Because the gating of the clocks can result in incom-
plete transactions, it is recommended that this option be used in applications where the SIO1 is not used or if reset
can be used to re-enable the SIO1 unit. Otherwise, the first transaction after re-enabling the unit might be
corrupted. Bit 6 of the powerc register (SIO2DIS) will power down the SIO2 unit.
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