Figure 11-3.Timing Diagram Example - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
JTAG Test Access Port
11.3 Elements of the JTAG Test Logic
11.3.2 The TAP Controller (continued)
It is very important in generating TAP input test signals to note that the actions resulting from a given state (such as
capture or shift) take place one clock cycle after the entry into that state. This requires one TCK cycle delay of the
TDI input bits with respect to the TMS input bits corresponding to the shift state. The timing diagram of
illustrates this point.
TCK
TMS 0
TAP
IDLE
CONTROLLER
STATE
TDI X
PARALLEL
OUTPUTS
OF TDR
TDO
Timing Description
The external controller drives TCK, TMS, and TDI (possibly through other devices). They all change state on the
falling edge of TCK. TDO is driven from the DSP and also changes on the falling edge of TCK. TMS and TDI are
strobed on the rising edge of TCK in the DSP, and the TAP Controller state changes just after the rising edge of
TCK.
Figure 11-3 shows two independent actions occurring: data parallel loaded into the test data register and shifted
out on TDO, and new data being shifted into the DSP test data register and then enabled to the parallel outputs of
TDR. In this example, the internal test data register is 4 bits long.
The sequence on TMS moves the TAP Controller through the states shown in
sequence 010 . . . changes the controller from IDLE, to select DR SCAN, to capture DR, etc. At the end of the cap-
ture DR state, data is parallel loaded into the test data register. On the next falling edge of TCK now in the Shift-DR
state, the LSB is shifted out of the DSP on TDO. On the next rising edge of TCK, the new data starts to shift into
the DSP from TDI. (TDI changes on the falling edge of TCK and the DSP strobes TDI on the rising edge.) After
four shifts, the new data is lined up in the DSP and is parallel loaded to the TDR output on the falling edge of TCK
in the middle of the UPDATE DR state.
11-6
(continued)
1 0 0
DR
CAPTURE
SCAN
DR
X X X
LSB
Figure 11-3. Timing Diagram Example
DRAFT COPY
0 0 0
SHIFT DR
0 1 0
MSB
TDR PARALLEL INPUTS
Figure
Information Manual
April 1998
Figure 11-3
1 1 0
EXIT
UPDATE
IDLE
DR
DR
1 X X
NEW DATA =
1 0 1 0
11-2. In this case, the
Lucent Technologies Inc.
5-4131