Hardware Development System (Hds) Module; Clock Synthesis (Dsp1627/28/29 Only); Power Management - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Hardware Architecture
2.11 Timer
(continued)
The timer interrupt can be individually enabled or disabled through the inc register. The timer can be stopped and
started by software and can be reloaded with a new delay at any time. The timer is fully described in Chapter 12,
Timer.

2.12 Hardware Development System (HDS) Module

The on-chip HDS performs instruction breakpointing and branch tracing at full speed. Through the JTAG port,
breakpointing is set up and the trace history is read back remotely. The JTAG port works in conjunction with HDS
code in the on-chip ROM and software in a remote computer.
Four hardware breakpoints can be set on instruction addresses. A counter can be preset with the number of
breakpoints to be received before trapping the core. Breakpoints can be set in interrupt service routines. Alter-
nately, the counter can be preset with the number of cache instructions to execute before trapping the core.
Every time the program branches instead of executing the next sequential instruction, the pair of addresses from
before and after the branch are caught in circular memory. The memory contains the last four pairs of program dis-
continuities for hardware tracing.
A multiprocessor feature can be configured, so all processors are trapped if one processor gets a breakpoint.
The Hardware Development System (HDS) is described in the DSP1600 Support Tools Manual and
DSP1611/17/18/27/28/29 supplements.

2.13 Clock Synthesis (DSP1627/28/29 Only)

The DSP1627/28/29 includes an on-chip clock synthesizer that can be used to generate the system clock for the
DSP. The clock will run at a programmable frequency multiple of the input clock (CKI). The 1X CKI input clock, the
output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal DSP clock.
On powerup, CKI is selected as the clock source for the DSP. Setting the appropriate bits in the pllc control regis-
ter will enable the clock synthesizer to become the clock source. The powerc register can override the selection to
stop clocks or force the use of the slow ring oscillator clock for low-power operation.
If not being used, the clock synthesizer can be powered down by clearing the PLLEN bit of the pllc register. Clock
synthesis is fully described in Section 3.5, Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)

2.14 Power Management

Many applications, such as portable cellular terminals, require programmable sleep modes for power management.
There are three different control mechanisms for achieving low-power operation: the powerc control register, the
STOP pin, and the AWAIT bit in the alf register. The AWAIT bit in the alf register allows the processor to go into a
power-saving standby mode until an interrupt occurs. The powerc register configures various power-saving
modes by controlling internal clocks and peripheral I/O units. The STOP pin controls the internal processor clock.
The various power management options can be chosen based on power consumption, wake-up latency require-
ments, or both. Power management is fully described in Section 3.6, Power Management.
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