Ad = Norm (As, Arm - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

aD = norm (aS, arM)

(arM) ← (# of redundant sign bits in aS); then
(aD) ← (aS) << (arM)
The exponent (E) of aS is computed and placed in arM. The 36-bit value in aS is then normalized based on this
exponent and placed in aD.
More specifically, this instruction performs the following two operations in sequence:
1. The number (E) of redundant sign bits present in the 36-bit value in aS is computed, extended to 16 bits, and
placed in arM. This exponent is generated with respect to bit 31 of aS. If an overflow has occurred, E will be
negative and an arithmetic right shift will be done to normalize the number. E = K – 5 where K is the total num-
ber of bits that are the same starting from bit 35 and counting to the right. For example:
Bit Positions
Accumulator Contents
2. The 36-bit value in aS is then arithmetically shifted left by E (the amount of this computed exponent), and the
36-bit shifted value is placed in aD. If aS has overflowed resulting in a negative exponent, the shift will be to the
right producing the correct normalized value in aD for this case.
The flags (described in Section 13.2.2, Shifting
The M field selects one of the four ar registers:
00 - ar0
Bit 15 14
Field 1 1
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(normalize aS)
35—32 31—0
0000 0110001 . . . 0
0000 0001100 . . . 0
0000 1000000 . . . 0
0110 1100010 . . . 0
1111 1100101 . . . 0
Operations) are set based on the value written into aD.
01 - ar1
13 12 11 10
1 1 0 D
Words: 1
Cycles: 1
Group: BMU
Addressing: Register
Flags affected: LMI, LEQ, LLV, LMV,
Interruptible: Yes
Cacheable: Yes
Format: 3b
DRAFT COPY
Normalization Action
K = 5, E = 0, no shifting required.
K = 7, E = 2, shift left twice.
K = 4, E = –1, shift right once.
K = 1, E = –4, shift right four times.
K = 6, E = 1, shift left once.
10 - ar2
9 8 7 6
S 0 0 0
ODDP, EVENP, MNS1, NMNS1
Instruction Set Summary
11 - ar3
5 4 3 2
0 1 1 1
1—0
M
B-50