Table 3-26. Phase-Locked Loop Control (Pllc) Register; Table 3-27. Pll Electrical Specifications And Pllc Register Settings - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
3.5.3 Latency (continued)

Table 3-26. Phase-Locked Loop Control (pllc) Register

Bit 15 14
Field PLLEN PLLSEL ICP SEL5V
Field Value
PLLEN 0
1
PLLSEL 0
1
ICP —
†
SEL5V 0
1
LF[3:0] —
Nbits[2:0] —
Mbits[4:0] —
† Not available on the DSP1628 or DSP1629.

Table 3-27. PLL Electrical Specifications and pllc Register Settings

M V
DD
23—24 2.7 V—3.6 V
21—22 2.7 V—3.6 V
19—20 2.7 V—3.6 V
16—18 2.7 V—3.6 V
12—15 2.7 V—3.6 V
8—11 2.7 V—3.6 V
2—7 2.7 V—3.6 V
5 V ± 5%
19—20
5 V ± 5%
17—18
5 V ± 5%
16
5 V ± 5%
14—15
5 V ± 5%
12—13
5 V ± 5%
10—11
5 V ± 5%
8—9
5 V ± 5%
7
5 V ± 5%
5—6
5 V ± 5%
2—4
Notes:
The M and N counter values in the pllc register must be set so that the VCO operates in the appropriate range
(see the data sheet). Choose the lowest value of N and then the appropriate value of M for
f = f x (M/(2N)) = f
INTERNAL CLOCK CKI
Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL out-
put clock is unstable. The DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the
PLL is locking. Completion of the lock-in interval is indicated by assertion of the LOCK flag.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
13 12 11—8
†
LF[3:0]
PLL powered down.
PLL powered up.
DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
Charge Pump Current Selection (see
3 V operation (see Table 3-27
5 V operation (see Table 3-27
Loop filter setting (see
Encodes N, 1 ≤ N ≤ 8; where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111 then N = 1.
Encodes M, 2 ≤ M ≤ 24; where M = Mbits[4:0] + 2 & f
pllc13 pllc12 pllc[11:8]
(ICP) (SEL5V)
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
/2.
VCO
DRAFT COPY
7—5
Nbits[2:0]
Description
Table 3-27
for proper value).
for proper value).
Table 3-27 for proper value).
Typical Lock-in Time (µs)
(LF[3:0]) (See Note 2)
1011
1010
1001
1000
0111
0110
0100
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
Software Architecture
(continued)
4—0
Mbits[4:0]
for proper value).
= f
INTERNAL CLOCK CKI
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
x (M/(2N)).
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