Table 4-12. Multiply/Alu Instructions - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
4.5 Instruction Set
4.5.5 Multiply/ALU Group (continued)
All multiply/ALU instructions require one word of memory. The number of instruction cycles required to execute an
instruction in the multiply/ALU group is a function of the statement selected from the transfer column in
Instructions with statements in the transfer column involving a write to RAM are executed in two instruction cycles
whether the instruction is in or out of the cache. Instructions with statements in the transfer column involving a read
from the X space and the Y space simultaneously are executed in two instruction cycles if not in the cache and one
instruction cycle if in the cache. An instruction with no transfer statement executes in one instruction cycle either in
or out of the cache. The remaining instructions are executed in one instruction cycle either in or out of the cache.
Table 4-12 gives the number of instruction cycles for each case.
The no operation (nop) instruction is a special-case encoding of a multiply/ALU instruction and is executed in one
instruction cycle. The assembly-language notation representation of a no operation instruction is either nop or a
single semicolon (;) and is assembled as *r0.
Note that the function statements and transfer statements in
statement can be combined with any transfer statement to form a valid multiply/ALU instruction. F1 function state-
ments and transfer statements can also be used alone to form valid instructions.

Table 4-12. Multiply/ALU Instructions

F1 Function Statements
p = x
aD = p p = x
aD = aS + p p = x
aD = aS – p p = x
aD = p
aD = aS + p
aD = aS – p
aD = y
aD = aS + y
aD = aS – y
aD = aS & y
aD = a S | y
aD = aS ^ y
aS – y
aS & y
† With a 2X clock selection, an instruction cycle is 2 times the period of the input clock (CKI). With a 1X clock selection, an
instruction cycle is 1 times the period of the input clock (CKI); or for the DSP1627/28/29, the instruction cycle is the fre-
quency of the clock source that is selected. If an external memory access is made in X or Y space and wait-states are
programmed, add the number of wait-states.
‡ Add one cycle if an X space access and a Y space access are made to the same bank of DPRAM in one instruction.
§ The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.
Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corresponding
CLR bit in the auc register is zero. auc is cleared by reset.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
Transfer Statements
y y = Y
*
y y = aT
*
§
y y[l] = Y
*
§
y aT[l] = Y
*
x = Y
Y
§
Y = y[l]
§
Y = aT[l]
Z : y
§
Z : y[l]
§
Z : aT[l]
DRAFT COPY
Table 4-12 are chosen independently. Any function
Cycles (Out/In Cache)
x = X 2/1
x = X 2/1
1/1
1/1
1/1
1/1
2/2
2/2
x = X 2/2
2/2
2/2
Instruction Set
Table
†
‡
‡
4-12.
4-23