Serial Interface #1 - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
15.2 Signal Descriptions
15.2.2 External Memory Interface (continued)
RWN
Read/Write Not: If a logic one, the pin indicates that the memory access is a read operation. If a logic zero, the
memory access is a write operation.
EXM
External Memory Select: Input only. This signal is latched into the device on the rising edge of RSTB. The value
of EXM latched-in determines if the internal ROM is addressable in the instruction/coefficient memory map. If EXM
is low, internal ROM is addressable. If EXM is high, only external ROM is addressable in the instruction/coefficient
memory map (see Section 3.2, Memory Space and
and MAP4.
EROM
External ROM Enable Signal: Negative assertion. If asserted, the signal indicates an access to external program
memory (see Section 3.2, Memory Space and
register (see Table 6-13).
ERAMHI
External RAM High Enable Signal: Negative assertion. If asserted, the signal indicates an access to external
data memory addresses 0x8000 through 0xFFFF (see
the ioc register (see Table
ERAMLO
External RAM Low Enable Signal: Negative assertion. If asserted, the signal indicates an access to external
data memory addresses 0x4100 through 0x7FFF (see
the ioc register (see Table
IO
External I/O Enable Signal: Negative assertion. If asserted, the signal indicates an access to external data mem-
ory addresses 0x4000 through 0x40FF (see
I/O. This signal's leading edge can be delayed via the ioc register (see
1
DSEL
Device Select Line: Default negative assertion (positive assertion is selectable via the ioc register, see
6-13). This signal predecodes a specific memory address in the I/O external memory segment. Access to location
1
0x4000 asserts DSEL as well as the external I/O enable.

15.2.3 Serial Interface #1

The serial interface pins implement a full-featured synchronous/asynchronous serial I/O channel. In addition, sev-
eral pins offer a glueless TDM interface for multiprocessing communication applications (see
1.DSEL not available in the DSP1627/28/29.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
Addressing). This signal's leading edge can be delayed via the ioc
6-13).
6-13).
Table 3-7). This memory segment is intended for memory-mapped
DRAFT COPY
Addressing). EXM chooses between MAP1, MAP2, MAP3,
Table 3-7). This signal's leading edge can be delayed via
Table 3-7). This signal's leading edge can be delayed via
Table
Interface Guide
6-13).
Figure 7-11).
Table
15-7