Eccp Interrupts And Flags; Traceback Ram - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
14.5 Software Architecture
14.5.2 ECCP Internal Memory-Mapped Registers (continued)
Complex Received Symbol Registers (ZIG10, ZQG32)
The complex received symbol registers are used for MLSE equalization. The complex received symbol is stored in
two registers in 10-bit two's complement form. The in-phase part of the received symbol is stored in the lower
10 bits of address location 0x40a, and the quadrature-phase part of the received symbol is stored in the lower 10
bits of address location 0x40B.
ZIG10 Bits
Function
ZQG32 Bits
Function
Reserved Registers
Addresses above 0x410 are reserved and should not be accessed by the user code. Specifically, a write to edr
with ear containing addresses higher than 0x410 can result in the incorrect operation of the ECCP.

14.5.3 ECCP Interrupts and Flags

The ECCP interrupts the DSP core with two vectored interrupts, and ECCP status is indicated with a user flag.
The ECCP user flag is named EBUSY and is used in conjunction with the if CON F2 or
if CON goto/call/return instructions to monitor the ECCP status during ECCP operation. The flag is defined as:

EBUSY: Asserted when the eir is written with an UpdateMLSE, UpdateConv, or TraceBack instruction and
negated when the ECCP instruction is completed. If the EBUSY flag is asserted, read operations of the edr reg-
ister and write operations to the eir and edr registers, including eir = ResetECCP, are ignored. Also, RAM4 can-
not be accessed.
Two vectored interrupts are EREADY and EOVF. These interrupts are maskable through the inc register, and their
status can be read or changed by using the ins register utilizing the DSP1600 interrupt conventions. An ireturn
from the vectored interrupt service routine will clear the interrupt status. (See
discussion.) The interrupts are defined as follows:

EREADY: Asserted three cycles before the EBUSY flag is negated. Negated upon writing a one in the EREADY
field of the ins register or upon executing an ireturn.

EOVF: An overflow condition is detected if any one of the next state registers is loaded with 0xFF in the eight
MSBs. This EOVF interrupt is then asserted to the DSP only after the current ECCP instruction is completed.
EOVF is negated upon writing a one in the EOVF field of the ins register or upon executing an ireturn instruc-
tion.

14.5.4 Traceback RAM

The fourth 1 Kword bank of dual-port RAM is shared by the ECCP for storing the traceback information. If the
ECCP is active (i.e., the EBUSY flag is asserted), the DSP core cannot access this traceback RAM, DSP write
operations to RAM4 are ignored, and read operations access corrupted data. As a rule, the DSP software must
avoid accessing RAM4 from either the X-memory space or Y-memory space if the eir register is written with one of
the UpdateMLSE, UpdateConv, or Traceback instructions. Following one of these instructions, the software can
determine the end of ECCP activity either by polling the EBUSY flag and waiting for its negation or by waiting for
the EREADY interrupt to be asserted. In the later case, RAM4 can be accessed by the EREADY interrupt service
routine.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Error Correction Coprocessor (DSP1618/28 Only)
(continued)
15—10
Reserved
15—10
Reserved
DRAFT COPY
9—0
ZI
9—0
ZQ
Section 3.4, Interrupts, for further
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