Data Move Instructions; Table 4-8. Data Move Instruction Summary - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
4.5 Instruction Set
4.5.2 Cache Instructions (continued)
Cache Statements
When the cache is used to repeat a block of N instructions, the cycle timing of the instructions are as follows:
1. The first pass does not affect cycle timing except for the last instruction in the block of N instructions. This
instruction always executes in two cycles, whether it is a one- or a two-cycle instruction.
2. During pass 2 through pass K – 1, each instruction is executed in the cache.
3. During the last (Kth) pass, the block of instructions executes inside the cache except for the last instruction that
executes outside the cache.
The instructions remain in the cache memory and can be reexecuted by using the redo command without the need
to reload the cache.

redo K. When the redo K instruction is used, the DSP executes the N instructions currently in the cache's mem-
ory K times. On the last iteration, the last instruction is executed outside the cache.
Control group instructions and instructions with 16-bit immediates cannot be executed from within the cache.
16-bit immediates can be found in data move, F3, and F4 instruction groups. The instruction set summary
(Appendix B) tells whether each instruction is cachable.
Note: Instructions in a cache loop are noninterruptible.

4.5.3 Data Move Instructions

Data move instructions perform three basic operations: moving immediate data to a register, moving data between
a register and an accumulator, and moving data between a register and Y-memory space. All data move instruc-
tions use one program location except for the long immediate instructions that use a second program memory word
for their immediate data. All execute in two instruction cycles except for the short immediate that executes in one
instruction cycle.

Table 4-8. Data Move Instruction Summary

Statement
R = IM16 Loads 16-bit immediate data (IM16) into a register (R).
SR = IM9 Loads 9-bit immediate data (IM9) into a YAAU register (SR).
R = aS[l] Loads contents of half of accumulator (aS[l] into a register (R).
aT[l] = R Loads contents of register (R) into half of accumulator (aS[l]).
R = Y Loads contents of memory location (Y) into a register (R).
Y = R Stores contents of register (R) into a memory location (Y).
Z : R Loads contents of memory location (Z) into a register (R), and
stores old contents of register (R) into memory location (Z).
DR = *(OFFSET) Loads contents of memory location (*(OFFSET)) into a register
(DR).
*(OFFSET) = DR Stores contents of a register (DR) into a memory location
(*(OFFSET)).
Note: If reading signed registers less than 16 bits wide, their contents are sign-extended to 16 bits. If reading
unsigned registers less then 16 bits wide, their contents are zero-extended to 16 bits. If short immediate
addressing is used to write to YAAU registers in the DSP, unsigned registers are zero-extended from 9 bits to
16 bits. Signed registers j and k are sign-extended from 9 bits to 16 bits.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
Description
DRAFT COPY
Instruction Set
Instruction Program
Cycles Locations
2 2
1 2
2 1
2 1
2 1
2 1
2 1
2 1
2 1
4-15