Figure 3-21.Power Management Using The Powerc Register (Dsp1627/28/29 Only) - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
3.6 Power Management
3.6.1 powerc Control Register Bits (continued)
XTLOFF
CKI2
OSCILLATOR,
SMALL SIGNAL
MASK-PROGRAMMABLE
CKI
CMOS
INPUT
CLOCK
STOP
HW STOP
NOCK
CLEAR NOCK
RSTB
INT0
INT0EN
INT1
INT1EN
Notes:
The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control regis-
ter. Bits used to power down peripheral units and the ECCP (DSP1628) are not shown.
Deep sleep is the state arrived at by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed to be clean in the sense that no partial clocks occur.
If the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered
down.
PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
Figure 3-21. Power Management Using the powerc Register (DSP1627/28/29 Only)
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
PLLEN
OFF
CRYSTAL
OR
CLOCK
OPTION
PLLSEL
DEEP
SLEEP
SW STOP
DISABLE
ON
RING
OSCILLATOR
f
slow clock
f /2
VCO
PLL
f
CKI
SYNC.
MUX
SYNC.
GATE
f
internal clock
INTERNAL
PROCESSOR
CLOCK
DRAFT COPY
Software Architecture
DEEP
SLEEP
SLOWCKI
5-4124.a
3-55