Motorola Mode, 16-Bit Read; Figure 9-4. Motorola Mode, 16-Bit Read - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
9.1 PHIF Operation
(continued)

9.1.3 Motorola Mode, 16-Bit Read

The external device drives PCSN, PRWN, PODS/PDS, and PIDS/PBSEL. The DSP drives PB.
In Motorola mode, PIDS is renamed PRWN (parallel read/write not) and selects a read or a write. PODS is
renamed PDS and is the data strobe for both input and output.
Initially, PB is 3-stated. The read operation is selected if PRWN is high during the transaction. Valid data is placed
on PB if both PCSN (chip select) and PDS (input data strobe) are low. The timing of this action is controlled by
whichever of the two goes low last. PBSEL (byte-select) is low, so the low byte from the pdx0(OUT) register is
placed on PB. If PDS is driven high by the external device, the data is latched externally and the DSP can again 3-
state the PB. The timing of this action is controlled by PDS or PCSN, whichever goes high first. PBSEL can now
be driven high to select the high byte of pdx0(OUT). The sense of PBSEL and PDS can be reversed by program-
ming the phifc register. The default state is shown here. The cycle is completed by another strobe from PCSN
and PDS. After the rising edge of PDS latches the high byte into the external device, the POBE interrupt is gener-
ated and the POBE output pin goes high.
PCSN
(CHIP SELECT)
PIDS/PRWN
†
PODS/PDS , FROM
EXTERNAL DEVICE
PBSE
PB, FROM DSP
†
POBE
LOW BYTE READ HIGH BYTE READ
† The logic levels of these pins can be inverted by programming the phifc register.
5-4497

Figure 9-4. Motorola Mode, 16-Bit Read

DRAFT COPY
Lucent Technologies Inc. 9-5