Interrupts; Introduction - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture

3.4 Interrupts

3.4.1 Introduction

If an interrupt condition arises (e.g., an I/O request like assertion of PIDS), a sequence of actions is taken by the
interrupt control logic to suspend normal program execution and branch to the interrupt service routine. The inter-
rupt service routine is executed before returning to the normal instruction.
Vectored interrupts allow multiple interrupt sources to be differentiated by assigning each to a unique interrupt
branching location. If more than one interrupt is asserted at the same time, they will be serviced sequentially
according to their assigned priorities. If an interrupt is being serviced and the same interrupt is requested again
before service of the first is completed, the interrupt must remain asserted until the next rising edge of IACK. The
interrupt structure of the DSP1611/17/27/29 provides a total of 11 interrupts and two traps, and the interrupt struc-
ture of the DSP1618/28 provides a total of 13 interrupts and two traps (see Table 3-20).
Interrupt service routines cannot be interrupted. Branch instructions, conditional branch instructions, postdecre-
ments of Y address registers, and cache loops are also not interruptible. A vectored interrupt that occurs during a
noninterruptible instruction is not serviced until after the next interruptible instruction has been executed.
A trap is similar to an interrupt except it gains control of the processor by branching to the trap service routine even
if the current instruction is noninterruptible. However, it might not be possible to return to the normal instruction
from the trap service routine because the state of the machine might not have been saved. The trap mechanism is
intended for two purposes. It can be used by an application to gain control of the processor rapidly for asynchro-
nous time-critical event handling (typically for catastrophic error recovery). It is also used by the hardware develop-
ment system (HDS) to gain control of the processor.
In the DSP1617, a set of interrupts have been retained to maintain compatibility with the DSP16A. Four I/O inter-
rupts and the hardware interrupt pin (INT0) from DSP16A can be used in a DSP16A-compatible mode (see Section
3.4.7, Interrupts in DSP16A-Compatible Mode (DSP1617 Only)).
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