Passive Mode; Peripheral Mode (Host Interface); Table 8-2. Function Of The Psel Pins - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel I/O (DSP1617 Only)
8.1 PIO Operation
(continued)

8.1.3 Passive Mode

In passive mode, the DSP can be used as a peripheral for other devices such as a microprocessor. Bits 12 and 11
of the pioc register configure the passive mode. If bit 12 of the pioc register is clear (0), the PODS signal becomes
an input and the contents of the DSP's parallel output register (pdx[OUT]) can be read by the external device
asserting PODS. If bit 11 of the pioc register is clear (0), PIDS is an input and the DSP's parallel input register
(pdx[IN]) can be written by the external device asserting PIDS.
Providing their respective interrupt mask bits are set (logic 1) in the pioc (or the inc register, see
rupts for more information), the assertion of PIDS (pioc bit 7) and PODS (pioc bit 6) by an external device causes
an interrupt to the DSP to become pending. This achieves functional synchronization between the DSP and an
external device.
The function of the three PSEL pins changes whenever PIO input or output is placed in passive mode.
shows the effects of various modes on the PSEL[2:0] bits.

Table 8-2. Function of the PSEL Pins

PODS PIDS
Active Active
Active Passive
Passive Active
Passive Passive
shows the complete encoding for PSEL[2:0] as outputs (000 corresponding to port pdx0, etc.).
Table 8-5
If passive mode is used for either input or output, PSEL2 becomes an active-low enable or chip select. While
PSEL2 is high, the DSP ignores any activity of a passive strobe. If a DSP using passive strobes is intended to be
continuously enabled, PSEL2 should be grounded.
Whenever PODS is passive, PSEL1 becomes an input that determines whether the PIO will drive PB with the con-
tents of pdx[OUT] (i.e., the data) or the contents of PSTAT (i.e., the PIO status).
If both PIDS and PODS are passive, PSEL0 takes on a special function. It is still an output, but it is now the logical
OR of the two PIO buffer flags (PIBF and POBE). This feature is useful if the user wishes to have one signal that
will tell an external device when the DSP is ready for a PIO access. (For further explanation, see
Peripheral Mode (Host Interface)).
8-6
PSEL2
Output (PSEL2)
Input (enable bar)
Input (enable bar)
Input (enable bar)
DRAFT COPY
PSEL1
Output (PSEL1)
Output (PSEL1)
Input (status/data)
Input (status/data) Output (PIBF | POBE)
Information Manual
April 1998
Section 3.4, Inter-
PSEL0
Output (PSEL0)
Output (PSEL0)
Output (PSEL0)
Section 8.1.4,
Lucent Technologies Inc.
Table 8-2