External Memory Interface - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Interface Guide
15.2 Signal Descriptions
15.2.1 System Interface (continued)
INT[1:0]
Processor Interrupts 0 and 1: Positive assertion. Hardware interrupt inputs to the DSP1611/17/18/27/28/29.
Each is enabled via the inc register. If enabled and asserted, each causes the processor to vector to the memory
location described in Table
junction with EXM to select the desired reset initialization of the mwait register (see
and RSTB is low, all output and bidirectional pins are put in a 3-state condition except for TDO which
3-states by JTAG control.
VEC[3:0]
Interrupt Output Vector: These four pins indicate the interrupt currently being serviced by the device.
shows the code associated with each interrupt condition. Pins VEC[3:0] are multiplexed with pins IOBIT[7:4].
IACK
Interrupt Acknowledge: Positive assertion. IACK signals if an interrupt is being serviced by the
DSP1611/17/18/27/28/29. IACK remains asserted while in an interrupt service routine and is cleared when the ire-
turn instruction is executed.
TRAP
Trap Signal: Positive assertion. If asserted, the processor is put into the trap condition that normally causes a
branch to the location 0x0046. The hardware development system (HDS) can configure the trap pin to cause an
HDS trap that causes a branch to location 0x0003. Although normally an input, the pin can be configured as an
output by the HDS. As an output, the pin can be used to signal a HDS breakpoint in a multiple processor environ-
ment.

15.2.2 External Memory Interface

The external memory interface is used to interface the DSP1611/17/18/27/28/29 to external memory and I/O
devices. It supports read/write operations from/to program and data memory spaces. The interface supports four
external memory segments. Each external memory segment can have an independent number of software-pro-
grammable wait-states. One hardware address is decoded and an enable line is provided to allow glueless I/O
interfacing. Because some instructions access X and Y memory simultaneously, a memory sequencer does the
simultaneous access to both X- and Y-memory space to avoid collisions (see
AB[15:0]
External Memory Address Bus: Output only. This 16-bit bus supplies the address for read or write operations to
the external memory or I/O.
DB[15:0]
External Memory Data Bus: This 16-bit bidirectional data bus is used for read or write operations to the external
memory or I/O.
1.DSP1617 only.
15-6
(continued)
3-20. INT0 can be enabled in the pioc for DSP16A compatibility
DRAFT COPY
Information Manual
April 1998
1
. INT1 is used in con-
Section 6.5). If INT0 is high
Section 6.6, Memory Sequencer).
Lucent Technologies Inc.
Table 3-18