Power Management Sequencing - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
3.6 Power Management

3.6.5 Power Management Sequencing

There are important considerations for sequencing the power management modes. Both the crystal oscillator and
the small-signal clock input circuits have start-up delays that must be taken into account. Also, the chip might or
might not need to be reset following a return from a low-power state.
Devices with the crystal oscillator or small-signal input clocking option can use the XTLOFF bit in the powerc reg-
ister to power down the on-chip oscillator or the small-signal circuitry, thereby, reducing the power dissipation.
When reenabling the oscillator or the small-signal circuitry, it is important to bear in mind that a start-up interval
exists during which time the clocks are not stable. Two scenarios exist here:
1. Immediate Turn-Off—Turn-On with RSTB: This scenario applies to situations where the target device is not
required to execute any code while the crystal oscillator or small-signal input circuit is powered down and where
restart from a reset state can be tolerated. In this case, the processor clock derived from either the oscillator or
the small-signal input is running if XTLOFF is asserted. This effectively stops the internal processor clock. If the
system chooses to reenable the oscillator or small-signal input, a reset of the device is required. The reset pulse
must be of sufficient duration for the oscillator start-up interval to be satisfied. A similar interval is required for
the small-signal input circuit to reach its dc operating point. A minimum reset pulse of 20 ms is adequate. The
falling edge of the reset signal (RSTB) asynchronously clears the XTLOFF field, thus, reenabling the power to
the oscillator or small-signal circuitry. The target DSP then starts execution from a reset state following the rising
edge of RSTB.
2. Running from Slow Clock While XTLOFF Active: This second scenario applies to situations where the device
needs to continue execution of its target code if the crystal oscillator or small-signal input is powered down. In
this case, the device switches to the slow ring oscillator clock first by enabling the SLOWCKI field before writing
a 1 to the XTLOFF field. Two nops are needed in between the two write operations to the powerc register. The
target device then continues execution of its code at slow speed while the crystal oscillator or small-signal input
clock is turned off. Switching from the slow clock back to the high-speed crystal oscillator clock is then accom-
plished in three user steps. First, XTLOFF is cleared. Then, a user-programmed routine sets the internal timer
to a delay to wait for the crystal's oscillations to become stable. When the timer counts down to zero, the high-
speed clock is selected by clearing the SLOWCKI field either in the timer's interrupt service routine or following a
timer polling loop.
For devices with the PLL and slow clock ring oscillator option, the use of the internal ring oscillator (slow clock) is
required if entering the low-power state. For reliable operation in all environments, the ring oscillator must be
selected as the clock source before the PLL is turned off.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
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Software Architecture
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