Phif Operation - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) April 1998

9.1 PHIF Operation

The PHIF is an asynchronous interface whose timing is controlled by an external host. The host initiates a read or
write of the port and controls the timing with the PIDS and PODS data strobes. The DSP program reacts to the
ensuing interrupt either by processing an interrupt service routine from an enabled interrupt or by polling the ins
(interrupt status) register to see if an interrupt has occurred.
The PHIF is compatible with two standard interfaces: one defined by Intel and one by Motorola . In the Intel mode,
PIDS is the input data strobe and PODS is the output data strobe with respect to the DSP. In Motorola mode, PIDS
is renamed PRWN (parallel read/write not) and selects between a read and a write. PODS is renamed PDS and
becomes the data strobe for both input and output.
Providing their respective interrupt mask bits are set (logic 1) in the inc register, the assertion of PIDS and PODS
by an external device causes a PIBF or POBE interrupt to the DSP to become pending. (See Section 3.4, Inter-
rupts, for more information.) PIBF and POBE are available at output pins and are used by the external host to
achieve functional synchronization with the DSP.
Pin Functions
This interface pin-multiplexes the parallel host interface with the second serial I/O interface and the 4-bit I/O inter-
face. The interface selection is made by writing the ESIO2 bit in the ioc register (see Section 9.4, PHIF Pin
Multiplexing). A zero value for ESIO2 selects the PHIF pins and is the default setting after device reset.
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