The Tap Controller - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 JTAG Test Access Port
11.3 Elements of the JTAG Test Logic
(continued)
11.3.1 The Test Access Port (TAP) (continued)
The timing diagram of Figure 11-3 illustrates some of the relationships among the TAP pins.
The TAP for the DSP1611/17/18/27 does not include the optional TRST (test reset) input that is used to initialize
the test logic to the inactive state. Instead, a built-in powerup reset circuit resets the test logic asynchronously to
the Test Logic Reset state of the TAP Controller (see Figure 11-1 and Figure 11-2) upon powering the device.
As mentioned before, the pull-up resistor on the TMS input drives a logic 1 to the unconnected TMS pin. The TAP
Controller reaches the test logic reset state (normal device function resumes) after receiving a logic 1 on TMS for
three to five TCK cycles. The pull-up resistor on TDI helps to isolate open-circuit faults of the scan path on a
board. An open TDO-to-TDI connection shifts a 1 into the device selecting the bypass register (instruction code
1111).

11.3.2 The TAP Controller

The TAP controller is a 16-state, finite-state machine implementing the state diagram of Figure 11-2. The value of
TMS (at the rising edge of TCK) controls the state transitions. Various instruction register and data register control
signals (such as shift, capture, and update), as well as boundary-scan control signals, are produced by the TAP
controller. These signals are combined with the instruction decoder outputs to select the active register and to con-
trol the operation of that register synchronously. The instruction register (JIR) is selected solely through the TAP
controller action, whereas test data registers (TDRs) are operated through the TAP controller and the instruction
decoder. A brief description of the TAP controller states follows:
Test Logic Reset: The test logic is disabled while the controller is in this state, so normal operation of the system
logic can proceed. The IDCODE instruction is asynchronously selected in the instruction register (JIR) if this state
is entered.
RUN Test/Idle: In the DSP1611/17/18/27/28/29, tests downloaded into the dual-port RAM for the purpose of self-
test should be executed in this state. Otherwise, this is an idle state and no changes in the state of the test logic
occur.
Select DR-Scan: This is a temporary state that is used to initiate the scanning of the test data register selected by
the current instruction.
Select IR-Scan: This is a temporary state that is used to initiate the scanning of the instruction register JIR.
Capture xR: Load from parallel inputs (if any) to the shift register stage of the selected register (JIR or one of the
TDRs). In this state, test results or control information is loaded into the shift register for subsequent scan opera-
tions.
Shift xR: In this state, data is shifted in the selected register one stage towards TDO on every rising edge of TCK.
Serial read and write of a register is performed in this state. Because the TDO output is enabled during the shift
state, a serial write operation (shifting into a register) is always accompanied by a serial read operation (shifting out
of a register) and vice versa.
Exit1 xR: This is a temporary state to choose between termination of the scanning operation and the pause state.
Pause xR: In this state, the shift operation is halted temporarily.
Exit2 xR: This is a temporary state to choose between resumption of the shift operation (after pause) and termina-
tion of the scanning operation.
Update xR: In this state, data from the shift register stage of the register is loaded into the latched parallel outputs
(if any) that remain stable during shift operations. This is the terminal state in a scan operation.
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