System Description; Error Correction Coprocessor (Dsp1618/28 Only) - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998

14 Error Correction Coprocessor (DSP1618/28 Only)

The error correction coprocessor (ECCP) performs full Viterbi decoding with single instructions for a wide range of
maximum likelihood sequence estimation (MLSE) equalization and convolutional decoding. The ECCP operates in
parallel with the DSP core increasing the throughput rate, and single-instruction Viterbi decoding provides signifi-
cant code compression required for a single DSP solution for modern digital cellular applications.

14.1 System Description

The ECCP is a loosely coupled, programmable internal coprocessor that operates in parallel with the DSP1600
core. Complete Viterbi decoding for MLSE equalization or convolutional decoding is performed with a single DSP
instruction.
The core communicates with the ECCP module via three interface registers. An address register (ear) is used to
indirectly access the ECCP internal memory-mapped registers. A data register (edr) works in concert with the
address register to indirectly read from or write to an ECCP internal memory-mapped register addressed by the
contents of the address register. After each edr access, the contents of the address register is postincremented by
one. Upon writing an ECCP opcode to instruction register eir, either MLSE equalization, convolutional decoding, a
simple traceback operation, or ECCP reset is invoked.
The mode of operation of the ECCP is set up by writing the appropriate fields of a memory-mapped control register.
In MLSE equalization, the control register can be configured for 2-tap to 6-tap equalization. In convolutional decod-
ing, the control register can be configured for constraint lengths 2 through 7 and code rates 1/1 through
1/6. One of two variants of the soft-decoded output can be programmed, or a hard-decoded output can be
chosen.
Usually, convolutional decoding is performed after MLSE equalization. For a receiver configuration with MLSE
equalization followed by convolutional decoding, a Manhattan branch metric computation for convolutional decod-
ing can be selected by setting a branch metric select bit in the control register.
In wideband low data rate applications, additive white Gaussian noise (AWGN) is the principle channel impairment.
Under these conditions, Euclidean branch metric computation for convolutional decoding is selected by resetting
the branch metric select bit to zero.
A traceback-length register is provided for programming the traceback decode length.
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