Table 14-2. Eccp Instruction Encoding; Table 14-3. Reset State Of Eccp Registers - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
14.5 Software Architecture
14.5.1 R-Field Registers (continued)
Data Register (edr): The contents of the ECCP internal memory-mapped registers are indirectly accessed by the
DSP through this register. A write to the data register is directed to the ECCP internal register addressed by the
contents of the ear register. A read from the data register fetches the contents of the ECCP internal register
addressed by the ear register. Every access to the edr increments the ear register.
Instruction Register (eir)
cuted upon writing appropriate values in the eir register.
mnemonics.

Table 14-2. ECCP Instruction Encoding

eir Value in Hex
0000
0001
0002
0003
0004
0005—FFFF
The UpdateMLSE instruction and the UpdateConv instruction each perform an appropriate branch metric calcula-
tion, a complete Viterbi add-compare-select operation, and a concurrent traceback decoding operation. The Trace-
Back instruction performs the traceback decoding alone. The ResetECCP instruction performs a proper reset
operation to initialize various registers as described in

Table 14-3. Reset State of ECCP Registers

Register
eir
ear
SYC
ECON
MIDX
MACH
MACL
During periods of ECCP activity, write operations to the eir and edr registers and read operations from the edr reg-
ister by the DSP code will be blocked. The eir register can be read during ECCP activity. The ECCP address reg-
ister, ear, can be read or written during ECCP activity to set up the ECCP address for the next edr access after the
completion of the ECCP instruction.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
:
Four instructions are defined for the ECCP operation. These instructions will be exe-
Instruction
UpdateMLSE
UpdateConv
TraceBack
Reserved
ResetECCP
Reserved
Reset State
0x4
0xF (on pin reset)
0x0
0x0
0x0
0x0
0xFF
0xFFFF
DRAFT COPY
Error Correction Coprocessor (DSP1618/28 Only)
Table 14-2 indicates the instruction encoding and their
Table 14-3.
14-9