Figure 3-20.Power Management Using The Powerc Register (Dsp1611/17/18 Only) - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Software Architecture
3.6 Power Management
3.6.1 powerc Control Register Bits (continued)
XTLOFF
CKI2
OSCILLATOR,
SMALL SIGNAL
CKI
TTL
INPUT
CLOCK
CMOS
INPUT
CLOCK
STOP
HW STOP
NOCK
RSTB
INT0
INT0EN
INT1
INT1EN
Notes:
The functions in the shaded ovals are bits in the powerc control register.
Bits used to power down the peripheral units and the ECCP (DSP1618 only) are not shown.
Deep sleep is the state arrived at by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed to be clean in the sense that no partial clocks occur.
If the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered
down.
Figure 3-20. Power Management Using the powerc Register (DSP1611/17/18 Only)
3-54
(continued)
OFF
CRYSTAL
OR
CLOCK
MASK
OPTION
SELECTION
DEEP
SLEEP
SW STOP
DISABLE
DRAFT COPY
ON
RING
OSCILLATOR
SYNC.
MUX
SYNC.
GATE
INTERNAL
PROCESSOR
CLOCK
CLEAR
NOCK
Information Manual
April 1998
DEEP
SLEEP
SLOWCKI
5-4124
Lucent Technologies Inc.