Motorola Mode, 16-Bit Write; Figure 9-5. Motorola Mode, 16-Bit Write - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
9.1 PHIF Operation

9.1.4 Motorola Mode, 16-Bit Write

The external device drives PCSN, PIDS/PRWN, PODS/PDS, PBSEL, and PB.
In Motorola mode, PIDS is renamed PRWN (parallel read/write not) and selects a read or a write. PODS is
renamed PDS and is the data strobe for both input and output.
Initially, PB is 3-stated. The write mode is selected if PIDS/PRWN is low, and the write is initiated by either PCSN
or PODS/PDS. Data is enabled into the DSP if both PCSN (chip select) and PODS/PDS (input data strobe) are
low. The timing of this action is controlled by whichever of the two goes low last. PBSEL (byte select) is low, so the
data is transferred to the low byte of the pdx0(IN) register. If PODS/PDS is driven high by the external device, the
data is latched by the DSP. The timing of this action is controlled by PODS/PDS or PCSN, whichever goes high
first. PBSEL can now be driven high to select the high byte of pdx0(IN). The sense of PBSEL and PODS/PDS can
be reversed by programming the phifc register. The default state is shown here. The cycle is completed by
another strobe from PCSN and PODS/PDS. After the rising edge of PODS/PDS latches the high byte into the DSP,
the PIBF interrupt is generated and the PIBF output pin goes high. The PIBF interrupt is reset when the DSP reads
pdx0(IN).
PCSN
(CHIP SELECT)
PIDS/PRWN
†
PODS/PDS , FROM
EXTERNAL DEVICE
†
PBSEL
PB, FROM
EXTERNAL DEVICE
PIBF †
† The logic levels of these pins can be inverted by programming the phifc register.
9-6
(continued)
LOW BYTE WRITE

Figure 9-5. Motorola Mode, 16-Bit Write

DRAFT COPY
Information Manual
April 1998
HIGH BYTE WRITE
5-4498
Lucent Technologies Inc.