Figure 2-7.Dsp1628 Block Diagram - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Hardware Architecture
2.1 Device Architecture Overview
2.1.3 Device Architecture (continued)
DB[15:0]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSTAT
OLD2 OR PODS
OCK2 OR PCSN
OBE2 OR POBE
SYNC2 OR PBSEL
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
† These registers are accessible through external pins only.
‡ DSP1628x16 contains a total of 16K x 16 internal RAM, and DSP1628x08 contains a total of 8K x 16 internal RAM.
2-8
(continued)
AB[15:0]
RWN EXM DSEL
ioc
EXTERNAL MEMORY INTERFACE & EMUX
ROM
48K x 16
DUAL-PORT
‡
RAM
15/7K x 16
XAB XDB YAB YDB
DSP1600 CORE
PHIF
phifc
† powerc
PSTAT
M
pdx0(IN)
U
X
pdx0(OUT)
Figure 2-7. DSP1628 Block Diagram
DRAFT COPY
I/O EROM ERAMHI ERAMLO
‡
RAM4
1K x 16
ECCP
eir
ear
edr
BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
CLOCK
SIO2
SYNTHESIZER
sdx2(OUT)
pllc
srta2
BIO
sbit
tdms2
cbit
sdx2(IN)
sioc2
saddx2
Information Manual
April 1998
JTAG
BOUNDARY-SCAN
jtag TDO
TDI
†
JCON
TCK
†
ID
TMS
†
BYPASS
TRST
HDS
†
BREAKPOINT
†
TRACE
TIMER
timerc
timer0
SIO1 DI1
ICK1
sdx(OUT)
ILD1
srta
IBF1
DO1
tdms
OCK1
OLD1
sdx(IN)
OBE1
sioc
SYNC1
SADD1
saddx
DOEN1
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