Table 5-4. Processor Status Word (Psw) Register; Control Registers - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Core Architecture
5.1 Data Arithmetic Unit
5.1.7 Control Registers (continued)
The accumulator guard bits are sign extended from bit 31 during data move instructions and, therefore, do not
affect the DAU flags. Writing the accumulator guard bits in the psw register will also change the corresponding bits
in the accumulator.

Table 5-4. Processor Status Word (psw) Register

Bit
15—12
Field
DAU Flags
Bit(s) Field
15—12 DAU Flags
11—10 X
9 a1[V]
8—5 a1[35—32]
4 a0[V]
3—0 a0[35—32]
† W indicates that the bit can be read or written.
‡ All DAU flags can be read from the psw register. The DAU flags are defined in
5-10
(continued)
11—10
X a1[V]
†
Value
‡
Wxxx LMI logical minus if set.
xWxx LEQ logical equal if set.
xxWx LLV logical overflow if set.
xxxW LMV mathematical overflow if set.
— Reserved.
W Accumulator 1 (a1) overflow if set.
Wxxx Accumulator 1 (a1) bit 35.
xWxx Accumulator 1 (a1) bit 34.
xxWx Accumulator 1 (a1) bit 33.
xxxW Accumulator 1 (a1) bit 32.
W Accumulator 0 (a0) overflow if set.
Wxxx Accumulator 0 (a0) bit 35.
xWxx Accumulator 0 (a0) bit 34.
xxWx Accumulator 0 (a0) bit 33.
xxxW Accumulator 0 (a0) bit 32.
DRAFT COPY
9 8—5
a1[35—32]
Result/Description
section 3.1.4 , on page
Information Manual
April 1998
4 3—0
a0[V] a0[35—32]
3-7.
Lucent Technologies Inc.