Table 2-1. Pipeline Flow For Concurrent Operations - Lucent Technologies DSP1617 Information Manual

Digital signal processor
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Information Manual
April 1998
2.1 Device Architecture Overview
2.1.2 Concurrent Operations (continued)
Table 2-1
shows the sequence of instructions whose operations are described in the previous example. The pipe-
lining of functional operations and data transfers is illustrated. The interpretation of the instructions is as follows:
y = Y means place the contents of memory space Y in register y. In the actual instruction, Y could be replaced by
*rM++. *rM++ denotes the memory location pointed to by the address in register rM (M = <0—3>) and postincre-
ment the address. Similarly, x = X means place the contents of memory space X in register x. In the actual
instruction, X could be replaced by *pt++. *pt++ denotes the memory location pointed to by the address in the pt
register and postincrement the address. p = x * y means multiply the data in registers x and y and put the result in
register p. a0 = a0 + p means add the value in p to the previous value in accumulator a0. The subscripts are
attached to indicate the order of the operation and to demonstrate the flow of the results of operations on y and x.
In this example, an accumulation takes place during every instruction cycle but there is a delay of three instructions
from the data into the x and y registers to the final accumulation.

Table 2-1. Pipeline Flow for Concurrent Operations

Instruction #
(1)
(2)
(3)
The most efficient programs use the parallelism as described above to the fullest extent. The instructions that
allow concurrent operations are the multiply/ALU instructions with their associated data transfers and are described
in detail in
Chapter
4,
Instruction
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
(continued)
Accumulator
a0
= a0
+ p
p
0
–1
0
a0
= a0
+ p
p
1
0
1
a0
= a0
+ p
p
2
1
2
Set.
DRAFT COPY
Multiplier
Registers
= x
* y
y
= Y
1
1
1
2
= x
* y
y
= Y
2
2
2
3
= x
* y
y
= Y
3
3
3
4
Hardware Architecture
, x
= X
2
2
2
, x
= X
3
3
3
, x
= X
4
4
4
2-3

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