Programmer Interface; Phifc Register Settings; Table 9-2. Parallel Host Interface Control (Phifc) Register - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)

9.2 Programmer Interface

The PHIF port can be accessed with any DSP instruction that reads or writes to pdx0 in the general group of
registers. The DSP reads the port by transferring data from the pdx0(IN) register and writes the port by transfer-
ring data to the pdx0(OUT) register. Although there are two separate physical registers (pdx0(IN) and
pdx0(OUT)), DSP instructions use the single syntax (pdx0) for both. The register that is accessed depends on
whether the register is read or written by the instruction:
a1=pdx0
pdx0=a1

9.2.1 phifc Register Settings

The PHIF control register (phifc) is a 16-bit user-accessible register used to configure some features of the PHIF
(see Table 9-2 and Table 9-3 on page
register are cleared resulting in the following default configuration: PHIF always enabled (PBSEL internally tied to
zero), Intel protocol, 8-bit transfers, pdx0 low byte selected (or PSTAT selected if PSTAT pin is asserted for a read
operation) if PBSL = 0, and the POBE flag is read through the PSTAT register as active-high.

Table 9-2. Parallel Host Interface Control (phifc) Register

Bit 15—7
Field
Reserved
Field Value
PSOBEF 0 Normal.
1 POBE flag as read through PSTAT register is active-low.
PFLAGSEL 0 Normal.
1 PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin unchanged.
PFLAG 0 PIBF and POBE pins active-high.
1 PIBF and POBE pins active-low.
PBSELF 0 If PBSEL pin = 0, pdx0 low byte
operation) is selected. (See
If PBSEL pin = 1, pdx0 low byte
1
operation) is selected. (See
PSTRB 0 If PSTROBE = 1, PODS pin (PDS) active-low.
1 If PSTROBE = 1, PODS pin (PDS) active-high.
PSTROBE 0 Intel protocol: PIDS and PODS data strobes.
1 Motorola protocol: PRWN and PDS data strobes.
PMODE 0 8-bit data transfers.
1 16-bit data transfers.
† See Table 9-3 on page 9 for selecting high byte.
9-8
/* Transfers data to the accumulator a1 from pdx0(in)
/* Transfers data from accumulator a1 to pdx0(out)
9). On powerup or if the RSTB signal is asserted, the contents of the phifc
PSOBEF PFLAGSEL PFLAG PBSELF PSTRB PSTROBE PMODE
DRAFT COPY
6 5 4
Description
†
(or PSTAT register if PSTAT pin is asserted for a read
Table 9-4 on page 11.)
†
(or PSTAT register if PSTAT pin is asserted for a read
Table 9-4 on page 11.)
Information Manual
April 1998
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Lucent Technologies Inc.
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