Figure 3-12.Interrupt Request Circuit Diagram - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Software Architecture
3.4 Interrupts
(continued)
3.4.4 Interrupt Operation (continued)
Concurrent Interrupts
If using DSP16A-compatible interrupts in the DSP1617 device, concurrent interrupts must be handled with extra
care in order to guarantee that all interrupts will be serviced (details are described in Section 4.2.6 of the DSP16A
Information Manual ). It is much simpler to handle concurrent interrupts if they are enabled from the inc register in
DSP1611/17/18/27/28/29. Interrupts are serviced according to the following rules:
If interrupt requests (internal or external) occur at the same time or pending interrupts are enabled at the same time
and the device is not servicing any of the pending requests, all the interrupts will be serviced sequentially according
to their priority. The corresponding interrupt status bit is cleared after that interrupt is serviced and ireturn is
issued. The interrupt service status pins (VEC[3:0]) and IACK pin indicate which interrupt is currently being ser-
viced. Figure 3-12 shows a typical circuit that is used to assert an interrupt by an external device. This circuit
removes the interrupt request signal when it begins to service that interrupt.
3-36
DSP1611/17/18/27/28/29
VEC0
VEC1
VEC2
VEC3
INT1
IACK
INT0
Q
Figure 3-12. Interrupt Request Circuit Diagram
DRAFT COPY
A0
Q0
A1
A2
1-OF-16
A3
DECODER
Q8
Q9
Q15
ENABLE
V
DD
D
INT1 INTERRUPT REQUEST
CK
CL
Information Manual
April 1998
INT1ACK
5-4147
Lucent Technologies Inc.