Interrupt Sources - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
3.4 Interrupts
(continued)

3.4.2 Interrupt Sources

1
There are 11 sources of interrupts and two sources of traps. The interrupt sources are described in the following
list; Table 3-20 has more detail for each interrupt vector's source, its vector address, its priority, its output encoding,
and its cause.

Software interrupt—An interrupt request issued by the instruction icall. The priority is 1 (lowest), and it is
nonmaskable. The icall instruction is reserved for use by the hardware development system.

IBF[2]
2
—Input buffer full indicates that an external device has written data into the SIO<1, 2> (serial input buffer).
IBF can be enabled from either pioc
are compatible with DSP16A, and their priority is lower than the vectored interrupts enabled from inc.

OBE[2]—Output buffer empty indicates that an external device has read data from the SIO<1, 2> (serial output
buffer). OBE can be enabled from either pioc

PIDS—Parallel input data strobe indicates that an external device has written data into the parallel input
register. PIDS can be enabled from either pioc

PODS—Parallel output data strobe indicates that an external device has read the data from the parallel output
register. PODS can be enabled from either pioc

PIBF—Parallel input buffer full flag indicates that data has been written to the parallel input data register. PIBF
can be enabled from inc.

POBE—Parallel output buffer empty flag indicates that the parallel output data register has been read by an
external device. POBE can be enabled from inc.

INT[1:0]—Interrupt by an external device indicates an external device has requested service by asserting the
INT[1:0] pin. INT0 can be enabled from either pioc

JINT—JTAG interrupt request indicates that the jtag register has been written. JINT is reserved for the hardware
development system.

TIMEOUT—Interrupt request by timer indicates that the timer has reached zero count.

EREADY
4
—Interrupt indicates ECCP is ready.

EOVF
4
—Interrupt indicates an ECCP overflow condition.
The interrupt sources can be classified in several different ways:

On- or off-chip: The INT[1:0], PIDS (passive), PODS (passive), and trap signals are externally generated; the
other interrupts are internally generated.

Hardware or software: The icall instruction generates a software interrupt; the rest are generated by hardware.

DSP16A—Compatible (DSP1617 only) or not: Four of the interrupt sources (PIDS, PODS, OBE, and IBF) have
a different effect depending on whether they are enabled from the pioc
enabled from the inc register. If they are enabled from the pioc
0x1. If they are enabled from the inc register, program control jumps to a different vector location for each. If
they are enabled from both the inc and the pioc
the INT0 is compatible with the INT of DSP16A because it vectors to location 0x1.
function of the DSP16A-compatible interrupts, and
1.13 for DSP1618/28.
2.The label in [ ] is optional; IBF[2] means IBF or IBF2.
3.DSP1617 only.
4.DSP1618/28 only.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
3
or inc (IBF2 can only be enabled from inc). Interrupts enabled from pioc
3
or inc (OBE2 can only be enabled from inc).
3
or inc.
3
or inc.
3
or inc.
3
registers, they are serviced as if enabled from the inc. Also,
Table 3-20
DRAFT COPY
Software Architecture
3
(DSP16A compatibility mode) or
3
register, program control will jump to location
Figure 3-9
describes them.
3
shows the logical
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