Figure 8-1.Parallel I/O Unit; Parallel I/O (Dsp1617 Only) - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

8 Parallel I/O (DSP1617 Only)

The DSP1617 Parallel I/O (PIO) is an 8-bit interface for rapid transfer of data with external devices. Data rates up
to 200 Mbits/s or 25 Mwords/s are supported by an instruction cycle of 20 ns. Minimal or no additional logic is
required to interface with memory or other peripheral devices. Five maskable interrupts are included in the PIO
unit. If not used, the PIO can be powered down via the powerc register. The PIO pins are multiplexed with BIO
and SIO2 pins, and selection is controlled from the ioc register (see
The PIO can operate in the active mode (data strobes provided by the DSP) or in the passive mode (data strobes
provided by an external device). As a passive port, the PIO acts as a flexible host interface requiring little or no
glue logic to interface to a host microcontroller, microprocessor, or DSP.
Although there is only one physical PIO port, there are eight logical PIO ports: pdx0 through pdx7. In active mode,
the state of the peripheral select pins PSEL[2:0] shows which logical port is selected.
The data path of the PIO is comprised of an 8-bit input buffer (pdx[IN]) and an 8-bit output buffer (pdx[OUT]).
Zeros are always returned in bits 15
(parallel output buffer empty), indicate the state of these buffers. The pdx[IN] register is shadowed in some modes
to allow the PIO to accept data on an interrupt without disrupting its normal operation (see
and the PIO). In addition, two registers control and monitor the PIO's operation: the PIO control (pioc) register and
the PIO status (PSTAT) register. PSTAT can only be read by an external device and reflects the condition of the
PIO. The pioc contains information about interrupts and can be used to set the PIO in a variety of modes. Access
times are programmable via the strobe field in the pioc.
PIDS
PB[7:0]
PODS
PSEL[2:1]
PSEL 0
PIBF
POBE
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
8 from a read of pdx. Two pins, PIBF (parallel input buffer full) and POBE
—
Figure 8-1
pdx[IN] (8)
SHADOW
pdx[OUT] (8)
pstat (3)
pioc (16)
Figure 8-1. Parallel I/O Unit
DRAFT COPY
Table 8-8).
Section 8.3, Interrupts
shows the DSP PIO unit at the block level.
PIO
16
16
16
IDB
5-4187
8-1