Elements Of The Jtag Test Logic; The Test Access Port (Tap) - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11.2 Overview of the JTAG Architecture
(continued)
The MODE column in Table 11-1 on page 3 refers to the value of the MODE control signal. The MODE control sig-
nal is obtained by merging the signals Input Mode Control and Output Mode Control, as defined in the standard,
into one signal. If Mode is 0, input signals into the device are from the input pins of the device and device output
signals are on the output pins. If Mode is 1, the device inputs and outputs are driven by the I/O scan path (the
JBSR). The Mode signal is further described in Section 11.3.4, The Boundary-Scan Register—JBSR.
All the mandatory instructions (BYPASS, SAMPLE, and EXTEST) and all optional instructions (IDCODE and
INTEST), as described in the standard, are implemented as Table 11-1 on page 3 shows. In addition, various read/
write instructions for accessing custom registers jtag and JCON in different modes of operation are used for self-
test and HDS.

11.3 Elements of the JTAG Test Logic

11.3.1 The Test Access Port (TAP)

The Test Access Port consists of three dedicated input pins (TCK, TMS, and TDI) and one dedicated output pin
(TDO). Additionally, the DSP1628/29 provides a TRST pin that can be used to reset the TAP controller. In a board
environment, TCK and TMS are usually broadcast signals driving all devices with a JTAG port in the same scan
path. TDI and TDO are usually daisy-chained among the devices by connecting the TDO of one device to the TDI
of another. Other configurations are also possible, and examples can be found in the IEEE document.
A description of the TAP pins follows:
TCK is the common test clock input pin that synchronizes test operations among the devices on a board. Synchro-
nization is essential for board interconnect tests and facilitates other test operations involving scanning various
registers. The TAP Controller as well as all the registers (instruction and test data) are clocked with TCK. Because
TCK is the common test clock in a board environment, the slowest JTAG design determines the common clock
frequency.
TMS is the test mode select input pin. It controls test operations by determining the current state of the TAP Con-
troller, for example, capturing test results or shifting data. All devices in a given scan path receive the same TMS
value and, thus, operate in the same state of the TAP Controller. The TMS value is sampled on the rising edge of
TCK. Normally, TMS changes on the falling edge of TCK providing half a clock cycle of setup time. Otherwise, the
external controller generating the TMS and TCK signals must allow enough setup time with respect to TCK. The
TMS pin has an internal pull-up resistor, as required by the standard, to apply a logic 1 to open TMS inputs.
TDI is the serial test data input pin. It provides the data for the instruction codes or test data register values needed
in the test and, like TMS, is sampled on the rising edge of TCK. Normally, the TDI signal is generated by the TDO
pin of the previous device on the chain (see TDO description below) and changes on the falling edge of TCK pro-
viding half a clock cycle of setup time. Otherwise, the source of TDI must allow enough setup time with respect to
TCK. The TDI pin is also internally pulled up to apply a logic 1 in case of an external open fault.
TDO is the 3-state serial test data output pin. It carries test results and other information out of the test logic while
in the Shift-DR state or Shift-IR state. During all other TAP Controller states, the TDO output is 3-stated. TDO
changes on the falling edge of TCK providing a convenient half clock cycle setup time for the TDI of the following
device. The register driving TDO is determined by the current instruction as well as the current TAP Controller
state. In the Shift-IR state, TDO is driven by the JIR register. During the Shift-DR state, one of the test data regis-
ters specified by the current instruction drives the TDO pin.
TRST 1
is the test logic reset input pin. If asserted low, TRST asynchronously resets the JTAG TAP controller. In an
application environment, this pin must be asserted prior to or concurrent with RSTB. This pin is internally pulled up
to avoid unwanted resetting of the TAP controller.
1.DSP1628/29 only.
DRAFT COPY
11-4 Lucent Technologies Inc.