Processor Flags - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

4.4 Processor Flags

Control and special function instructions can be conditionally executed on the basis of internal flags set by the fol-
lowing conditions:

A previous ALU operation

A previous BMU operation

A previous special function instruction

The condition of one of the counters

The value of a randomly set bit

A test by the BIO port

An interrupt from the JTAG port
Functional operations on the accumulators set the flags as described above. Loading the accumulators with data
move instructions or multiply/ALU transfer statements does not set flags.
Four of the basic processor flags are defined below. They can be set by either ALU or BMU operations. These
flags and their meanings are given below:
LMI Logical Minus—A logical minus is determined by the state of bit 35 of the accumulator after the last DAU or
BMU operation result. If bit 35 = 1, the result is a negative number and LMI is true.
LEQ Logical Equal—A logical equal is determined by testing bits 35—0 of the last DAU or BMU operation
result. If these bits are all zero, the result is zero and LEQ is true.
LLV Logical Overflow (36-bit Overflow)—LLV is true if the sign of the result of an operation cannot be repre-
sented in a 36-bit accumulator.
LMV Mathematical Overflow (32-bit Overflow)—LMV is true if bit 31 of the accumulator differs from any of the
guard bits (32—35) after the last DAU or BMU operation. This indicates a number not representable in
32 bits.
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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
DRAFT COPY
Instruction Set
4-9