Hardware View; Figure 12-1.Timer Block Diagram; Chapter 12. Timer - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
12 Timer
The timer is an internal counter controlled by instructions that write to two control registers. The output of the timer
is an interrupt to the core processor. The timer can be configured to count down once and interrupt or to interrupt
regularly at a programmed interval. With a DSP instruction cycle of 20 ns, the interrupt interval can be set from
40 ns to over 85 seconds.

12.1 Hardware View

8
IDB
Figure 12-1 is a block diagram of the timer. The interface to the DSP core is through the internal data bus (IDB)
and through the interrupt (TIMEOUT). There are four main blocks in the timer (the timer control register timerc, the
prescaler, the 16-bit down-counter, and the period register). The timer control register (timerc) is an 8-bit register
written over the IDB. Bits 0—3 are the prescale number (N) that divides the CKO clock by 2
the timer0. Bit 4 (T0EN) enables the CKO to the prescaler. Bit 5 (RELOAD) selects the one-time or the repeated
operation. Bit 6 (DISABLE) powers down the timer for reduced power in sleep mode. Bit 4 in the powerc register
(TIMERDIS) performs the same function, i.e., powering down the timer. Bit 7 can be read and written, but it has no
effect. Bits 8—15 are not implemented in the register but should be written with zeros to make the code compatible
with future device versions. The prescaler divides the CKO frequency by the number 2
number from 0 to 15. The timer, addressed as timer0, is a 16-bit down-counter that can be loaded from program
memory over the IDB bus. It then counts down to zero at the clock rate provided by the prescaler. Upon reaching
zero, the TIME interrupt is issued to the DSP core. The timer will then either wait in a quiescent state for another
command or will automatically repeat the last interrupting period corresponding to RELOAD (bit 5 in timerc). The
timer0 register can also be read over the IDB bus at any time transferring the current state of the counter. The
period register stores the beginning count for the repeat mode and is loaded by a write to timer0.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
timerc
0
PRESCALE
3
CKO
T0EN 4
RELOAD 5
6
DISABLE
RESERVED
7
PERIOD
REGISTER
INITIAL
COUNT
16
Figure 12-1. Timer Block Diagram
DRAFT COPY
N 4
PRESCALE
DIV. BY 2
2 to 65536
CONTROL
timer0
16-bit
COUNTER
N + 1
TCLK
TIMEOUT
INTERRUPT
N + 1
before it goes to
N + 1
where N is a binary
5-4210
12-1