Normalization - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Bit Manipulation Unit
13.2 Software View
13.2.2 Shifting Operations (continued)
LMV Logical Mathematical Overflow—LMV is true if any of the accumulator bits 35—31 are different after the
shift operation. Stored in bit 12 of the psw register.
Four additional flags are also set from BMU operations:
evenp Even Parity—True if all bits (35—0) have even parity. Stored in bit 5 of the alf register.
oddp Odd Parity—True if all bits (35—0) have odd parity. Stored in bit 4 of the alf register.
mns1 Minus 1—True if all bits (35—0) are 1s (minus one in two's complement). Stored in bit 6 of the alf register.
nmns1 Not Minus 1—True for all other patterns other than all 1s. Stored in bit 7 of the alf register.

13.2.3 Normalization

A two's complement number is normalized by detecting the number (E) of extra (or redundant) sign bits and then
shifting the number to the left E times. For example:
There are three extra sign bits, so shift left three times in order that the last sign bit ends up in the MSB position.
For the DSP, the number (E) of redundant sign bits is found with respect to sign bit 31. If an overflow has occurred,
E will be negative and an arithmetic right shift will be done to normalize the number. E = K – 5 where K is the total
number of bits that are the same starting from bit 35 and counting to the right. For example:
Bit Positions
Accumulator Contents
The instruction for exponentiation is aD = exp (aS) where the exponent (E) is placed in the high half of the destina-
tion accumulator (aD, bits 31—16). The lower half (bits 15—0) is cleared.
The instruction for normalization is aD = norm (aS, arM) where the exponent (E) is calculated and placed in one of
the arM (M = 0, 1, 2, or 3) registers. The number in aS is normalized and placed in aD with the sign bit in bit 31.
aS is left unchanged.
The flags (described Section 13.2.2, Shifting
13-4
(continued)
35—32 31—0
0000 0110001 . . . 0
0000 0001100 . . . 0
0000 1000000 . . . 0
0110 1100010 . . . 0
1111 1100101 . . . 0
Operations) are set based on the value written into aD.
DRAFT COPY
11110011
10011000
Normalization Action
K = 5, E = 0, no shifting required.
K = 7, E = 2, shift left twice.
K = 4, E = –1, shift right once.
K = 1, E = –4, shift right four times.
K = 6, E = 1, shift left once.
Information Manual
April 1998
Lucent Technologies Inc.