Figure 3-14.Timing Diagram Of User Trap - Lucent Technologies DSP1617 Information Manual

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Software Architecture
3.4 Interrupts
(continued)
3.4.5 Trap Description (continued)
†
CKO
USER TRAP
IACK
VEC[3:0]
A B C D E F
5-4119.a
† CKO is a zero-wait-stated clock.
Notes:
A. TRAP pin is synchronized and latched in interrupt pending latch.
B. A constant two-cycle delay to allow a two-cycle instruction to complete before entering into the trap service routine.
C. Branch to trap service routine.
D. Start executing instructions in trap service routine.
E. ireturn instruction is executed; end of trap service routine.
F. Next interruptible instruction.
Figure 3-14. Timing Diagram of User Trap
DRAFT COPY
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