Bit Manipulation Unit (Bmu); Hardware View; Figure 13-1.Bmu Block Diagram; Chapter 13. Bit Manipulation Unit - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998

13 Bit Manipulation Unit (BMU)

The BMU has powerful bit manipulation capabilities. A general 36-bit barrel shifter interfaces directly to the main
accumulators in the DAU providing the following features:

Barrel shifting—logical and arithmetic, left and right shift

Normalization and extraction of exponent

Bit-field extraction and insertion
These features increase the efficiency of the DSP in applications such as control or data encoding/decoding. For
example, data packing and unpacking, in which short data words are packed into one 16-bit word for more efficient
memory storage, are very easy.
In addition, the BMU provides two auxiliary accumulators. In one instruction cycle, 36-bit data can be shuffled or
swapped between one of the main accumulators and one of the alternate accumulators.

13.1 Hardware View

Figure 13-1 is the block diagram of the BMU. The BMU components are shown shaded with the components in the
DSP core (the main accumulators and the data bus (IDB)) shown to the left. The ar<0—3> registers are 16-bit reg-
isters that control the operations of the BMU. They store a value that determines the amount of shift or the width
and offset fields for bit extraction or insertion. Alternately, an immediate data word transferred over the IDB can
control the above operations. The third input to the MUX, the upper half of one of the main accumulators (bits
31—16), can determine the amount of shift but is not used as a control in the extraction/insertion instructions. The
BMU operational unit performs not only full-barrel shift operations but the related operations of extraction, insertion,
normalization, and extraction of exponent. The operational unit has a full 36-bit bidirectional data bus to the main
accumulators (a0 and a1) in the DAU. Certain operations in the operational unit set flags that are returned to the
DSP core. The final block in the BMU contains the 36-bit alternate accumulators aa0 and aa1. In one instruction
cycle, data can be shuffled between one of the main accumulators and one of the alternate accumulators.
The arM registers can be used as general-purpose registers that are read and written with data move instructions.
a0, a1
MAIN ACCUMULATORS
IN DAU
nmns1, mns1, oddp, evenp
LMI, LEQ, LLV, LMV
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
aa0, aa1
36
ALTERNATE
ACCUMULATORS
FLAGS
Figure 13-1. BMU Block Diagram
DRAFT COPY
16
16
36
4
4
ar0, ar1,
ar2, ar3
REGISTERS
EXP
MUX
CONTROL
BMU SHIFT,
EXTRACT, INSERT,
NORMALIZE, FIND
EXPONENT
5-4212
13-1