Table Of Contents - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 Digital Signal Processor
1 Introduction.................................................................................................................................................. 1-1
1.1 General Description .......................................................................................................................... 1-2
1.1.1 Architecture ........................................................................................................................ 1-2
1.1.2 Instruction Set .................................................................................................................... 1-3
1.2 Typical Applications........................................................................................................................... 1-3
1.3 Application Support........................................................................................................................... 1-4
1.3.1 Support Software Library ................................................................................................... 1-4
1.3.2 Hardware Development System ......................................................................................... 1-4
1.4 Manual Organization ......................................................................................................................... 1-6
1.4.1 Applicable Documentation ................................................................................................. 1-7
2 Hardware Architecture................................................................................................................................. 2-1
2.1 Device Architecture Overview ........................................................................................................... 2-1
2.1.1 Harvard Architecture .......................................................................................................... 2-1
2.1.2 Concurrent Operations ....................................................................................................... 2-2
2.1.3 Device Architecture ............................................................................................................ 2-4
2.1.4 Memory Space and Bank Switching ................................................................................ 2-12
2.1.5 Internal Instruction Pipeline .............................................................................................. 2-13
2.2 Core Architecture Overview ............................................................................................................ 2-16
2.2.1 Data Arithmetic Unit ......................................................................................................... 2-16
2.2.2 Y Space Address Arithmetic Unit (YAAU) ........................................................................ 2-17
2.2.3 X Space Address Arithmetic Unit (XAAU) ........................................................................ 2-18
2.2.4 Cache ............................................................................................................................... 2-18
2.2.5 Control ............................................................................................................................. 2-18
2.3 Internal Memories ........................................................................................................................... 2-19
2.4 External Memory Interface (EMI) .................................................................................................... 2-19
2.5 Bit Manipulation Unit (BMU)............................................................................................................ 2-20
2.6 Serial Input/Output (SIO) Units ....................................................................................................... 2-20
2.7 Parallel Input/Output (PIO) (DSP1617 Only)................................................................................... 2-21
2.8 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) .......................................................... 2-21
2.9 Bit Input/Output (BIO) ..................................................................................................................... 2-22
2.10 JTAG ............................................................................................................................................... 2-22
2.11 Timer ............................................................................................................................................... 2-22
2.12 Hardware Development System (HDS) Module.............................................................................. 2-23
2.13 Clock Synthesis (DSP1627/28/29 Only) ......................................................................................... 2-23
2.14 Power Management ........................................................................................................................ 2-23
3 Software Architecture .................................................................................................................................. 3-1
3.1 Register View of the DSP1611/17/18/27/28/29................................................................................. 3-1
3.1.1 Types of Registers .............................................................................................................. 3-1
3.1.2 Register Length Definition .................................................................................................. 3-5
3.1.3 Register Reset Values ........................................................................................................ 3-6
3.1.4 Flags .................................................................................................................................. 3-7
3.2 Memory Space and Addressing........................................................................................................ 3-8
3.2.1 Y-Memory Space ................................................................................................................ 3-8
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INFORMATION MANUAL
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Lucent Technologies Inc.