Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information.

MN97-030WDSP

DSP1611/17/18/27/28/29

Digital Signal Processor

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DRAFT COPY

Table of Contents

Chapters

Table of Contents

Summary of Contents for Lucent Technologies DSP1617

Page 1 ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Page 2 Tapdance FlashDSP The following trademarks, owned by entities other than Lucent Technologies Inc., are used in this manual: IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Intel is a registered trademark of Intel Corporation.
Page 3 Signal Processor family, which includes the FlashDSP 1618, FlashDSP 1627, FlashDSP 1628, and FlashDSP 1629 development devices. The DSP1611-ST, DSP1618-ST, DSP1617-ST, DSP1627-ST, DSP1628-ST, and DSP1629-ST support software libraries, the FlashDSP 1600-HDS Development System, and numerous DSP1611/17/18/27/28/29-specific hardware support tools are also available to aid in developing soft- ware and integrating the devices into systems.
Page 4: Table Of Contents
External Memory Interface (EMI) ....................2-19 Bit Manipulation Unit (BMU)......................2-20 Serial Input/Output (SIO) Units ....................... 2-20 Parallel Input/Output (PIO) (DSP1617 Only)................... 2-21 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) ............2-21 Bit Input/Output (BIO) ........................2-22 2.10 JTAG ............................... 2-22 2.11 Timer ...............................
Page 5 3.4.5 Trap Description ....................... 3-38 3.4.6 Powerdown with the AWAIT State ..................3-40 3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) ..........3-42 3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) ........3-44 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)............3-47 3.5.1 PLL Control Signals ......................
Page 6 Detailed Multiprocessor Mode Description ..............7-17 7.6.3 Suggested Multiprocessor Configuration ................. 7-24 7.6.4 Multiprocessor Mode Initialization ..................7-25 Serial Interface #2 ........................... 7-26 7.7.1 SIO2 Features ........................7-26 7.7.2 Programmable Features ....................7-27 7.7.3 Instructions Using the SIO2 ..................... 7-27 Lucent Technologies Inc.
Page 7 8 Parallel I/O (DSP1617 Only)........................8-1 PIO Operation ........................... 8-2 8.1.1 Active Mode ........................8-2 8.1.2 PIO Interaccess Timing ...................... 8-5 8.1.3 Passive Mode ........................8-6 8.1.4 Peripheral Mode (Host Interface) ..................8-9 Programmer Interface ........................8-14 8.2.1 pioc Register Settings ..................... 8-16 8.2.2...
Page 8 UpdateMLSE Instruction with Soft Decision ..............14-19 14.6.3 UpdateMLSE Instruction with Hard Decision ..............14-21 14.6.4 UpdateConv Instruction with Soft Decisions ..............14-22 14.6.5 UpdateConv Instruction with Hard Decision ..............14-23 14.6.6 TraceBack Instruction ..................... 14-23 viii Lucent Technologies Inc.
Page 9 15.4 Mask-Programmable Options ....................... 15-14 15.4.1 Input Clock Options ......................15-14 15.4.2 ROM Security Options (DSP1617/18/27/28/29 Only) ............ 15-14 15.5 Additional Electrical Characteristics and Requirements for Crystal ..........15-15 A Instruction Encoding............................ A-1 Instruction Encoding Formats ......................A-1 Field Descriptions ..........................A-4 B Instruction Set Summary ..........................
Page 10 = extractz (aS, arM) ..........................B-51 aD = extracts (aS, IM16) .......................... B-52 aD = extractz (aS, IM16) .......................... B-52 aD = insert (aS, arM)..........................B-53 aD = insert (aS, IM16) ..........................B-54 aD = aS : aaT ............................B-55 Lucent Technologies Inc.
Page 11 Figure 3-6.p Register to Accumulator Bit Alignment, auc[1:0] = 10 ............... 3-25 Figure 3-7.Register to Accumulator Bit Alignment, auc[1:0] = 11 ..............3-26 Figure 3-8.Interrupt Operation ........................3-28 Figure 3-9.DSP16A-Compatible Interrupts (DSP1617 Only) ................. 3-30 Figure 3-10.Timing Diagram of a Simple Interrupt ..................3-33 Figure 3-11.Interrupt Disable Latency ......................3-35 Figure 3-12.Interrupt Request Circuit Diagram ....................
Page 12 Figure 7-7.SIO Active Mode Output Timing, 16-bit Words ................7-7 Figure 7-8.SIO Passive Mode Output Timing, 8-bit Words................7-8 Figure 7-9.DSP1611/17/18/27/28/29 to Lucent Technologies CSP1027 Codec Interface ......7-13 Figure 7-10.DSP1611/17/18/27/28/29 to Lucent Technologies T7525 Codec Interface ....... 7-13 Figure 7-11.Multiprocessor Connections ....................... 7-15 Figure 7-12.Destination Address Communication ..................
Page 13 Figure 13-7.Insertion, Case 2. Source and Destination Accumulators Are the Same ........13-7 Figure 13-8.Shuffle Accumulators ......................... 13-8 Figure 14-1.Error Correction Coprocessor Block Diagram/Programming Model........... 14-2 Figure 14-2.DSP Core Operation Sequence ....................14-6 Figure 14-3.ECCP Operation Sequence ....................... 14-7 Figure 14-4.Register Block Diagram......................14-8 xiii Lucent Technologies Inc.
Page 14 Table 3-8. DSP1611 Instruction/Coefficient Memory Map (X-Memory Space) ......... 3-11 Table 3-9. DSP1617 Instruction/Coefficient Memory Map (X-Memory Space) ......... 3-12 Table 3-10. DSP1618 Instruction/Coefficient Memory Map (X-Memory Space) ......... 3-12 Table 3-11. DSP1618x24 Instruction/Coefficient Memory Map (X-Memory Space) ........3-13 Table 3-12.
Page 15 Table 6-15. Index of Timing Examples......................6-17 Table 6-16. Data Memory Map (DSP1617 Only) ..................6-28 Table 7-1. Serial I/O Control (sioc) Register (DSP1611, DSP1617, and DSP1618 Only) ......7-9 Table 7-2. Serial I/O Control (sioc) Register (DSP1627/28/29 Only) ............7-9 Table 7-3.
Page 16 Table 11-3. JTAG Scan Register (DSP1611, 1617 and 1618 Only) ............11-9 Table 11-4. JTAG Scan Register (DSP1627/28/29 Only) ................11-10 Table 11-5. JIDR Field Descriptions DSP1617/18/27/28/29 ..............11-17 Table 11-6. JIDR Field Descriptions DSP1611 ..................11-18 Table 12-1. timerc Register ......................... 12-2 Table 13-1.
Page 17 Table A-17. X Field ............................A-10 Table A-18. Y Field ............................A-10 Table A-19. Z Field ............................A-10 Table B-1. CON Field Encoding ........................B-3 Table B-2. R Field Replacement Values....................... B-8 Lucent Technologies Inc. xvii...
Page 18: Introduction
Chapter 1 Introduction...
Page 19 CHAPTER 1. INTRODUCTION CONTENTS 1 Introduction ..............................1-1 General Description ...........................1-2 1.1.1 Architecture .........................1-2 1.1.2 Instruction Set ........................1-3 Typical Applications ...........................1-3 Application Support ...........................1-4 1.3.1 Support Software Library ....................1-4 1.3.2 Hardware Development System ..................1-4 Manual Organization..........................1-6 1.4.1 Applicable Documentation ....................1-7...
Page 20 Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 1 Introduction Designed specifically for applications requiring low-power dissipation in digital cellular systems, the DSP1611, DSP1617, DSP1618, DSP1618x24 , DSP1627, DSP1627x32 , DSP1628x08 , DSP1628x16 , DSP1629x10 , and DSP1629x16 are signal coding devices that can be programmed to perform a wide variety of fixed-point signal processing functions.
Page 21: General Description
1.1 General Description 1.1.1 Architecture The DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 are made up of the DSP1600 core pro- cessor, a dual-port RAM, ROM, and several peripheral blocks. The core contains the data arithmetic unit, the memory addressing units, the cache, and the control section.
Page 22: Instruction Set
Tone detection, tone generation, MF, DTMF Switches Tone detection, tone generation, line testing Transmission Multipulse LPC, ADPCM, transmultiplexing, encryption, DS0, DS1 1.XX denotes the last two digits of the device name, e.g., XX = 11 for the DSP1611. DRAFT COPY Lucent Technologies Inc.
Page 23: Application Support
Software development tools to help create, test, and debug DSP1611/17/18/27/28/29 application programs are available from the Lucent Technologies’ appropriate support software library for the particular device. Each sup- port software library consists of an assembler, linker, and software simulator that run on Sun-4...
Page 24: Figure 1-1.In-Circuit Emulation With The Flashdsp 1600-Jcs
Another development tool available is the demonstration board (DSP1611/17/18/27/28/29-DEMO). The demon- stration board replaces the customer board in Figure 1-1 and provides a development platform with external mem- ory (static RAM or PROM), a DSP1611/17/18/27/28/29 device, and access many DSP signals. DRAFT COPY Lucent Technologies Inc.
Page 25: Manual Organization
April 1998 1.4 Manual Organization This document is a reference guide for the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629. It describes the architecture, instruction set, and interfacing requirements of the device. The remaining chapters of this manual are outlined below:...
Page 26: Applicable Documentation
A variety of documents exists to provide specific information on various members of the DSP1600 product family. Contact your Lucent Technologies Account Manager for the latest issue of any of the following documents. The back cover lists contact numbers for customer assistance.
Page 27: Hardware Architecture
Chapter 2 Hardware Architecture...
Page 28 Control ..........................2-18 Internal Memories ..........................2-19 External Memory Interface (EMI).....................2-19 Bit Manipulation Unit (BMU) ......................2-20 Serial Input/Output (SIO) Units ......................2-20 Parallel Input/Output (PIO) (DSP1617 Only) ...................2-21 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) ............2-21 Bit Input/Output (BIO) ........................2-22 2.10 JTAG ..............................2-22 2.11 Timer..............................2-22 2.12 Hardware Development System (HDS) Module................2-23...
Page 29: Device Architecture Overview
April 1998 2 Hardware Architecture This chapter presents an overview of the hardware in the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629. First, an overall view of the architecture is discussed; then, each major functional block is described. The following chapters give full details on each block.
Page 30: Concurrent Operations
In fact, a multiplication can occur in parallel with a variety of ALU operations. INTERNAL CACHE CONTROL INSTRUCTIONS DUAL-PORT DUAL-PORT XAAU YAAU BANK 4 BANK 1 VARIABLE DATA COEFFICIENTS y REGISTER x REGISTER MULTIPLIER ACCUMULATOR 5-4141.a Figure 2-2. Concurrent Operations in the DSP1611/17/18/27/28/29 DRAFT COPY Lucent Technologies Inc.
Page 31: Table 2-1. Pipeline Flow For Concurrent Operations
The most efficient programs use the parallelism as described above to the fullest extent. The instructions that allow concurrent operations are the multiply/ALU instructions with their associated data transfers and are described in detail in Chapter Instruction Set. DRAFT COPY Lucent Technologies Inc.
Page 32: Figure 2-3.Dsp1611 Block Diagram
Figures 2-3, 2-4, 2-5, 2-6, 2-7, and show the block diagrams for DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 processors. The major blocks are the DSP1600 processor core, the memories, the bit manipulation unit, the external memory interface, the serial input(s)/output(s), the parallel input/output, the bit I/O, the JTAG, and the timer.
Page 33: Figure 2-4.Dsp1617 Block Diagram
SYNC1 IBF2 OR PIBF cbit sdx2(IN) SADD1 DOEN2 OR PB2 saddx sioc2 DOEN1 SADD2 OR PB3 IOBIT[3:0] OR PB[7:4] saddx2 † These registers are accessible through external pins only. 5-4142.b Figure 2-4. DSP1617 Block Diagram DRAFT COPY Lucent Technologies Inc.
Page 34: Figure 2-5.Dsp1618 Block Diagram
DOEN2 OR PB2 saddx sioc2 DOEN1 SADD2 OR PB3 saddx2 IOBIT[3:0] OR PB[7:4] † These registers are accessible through external pins only. ‡ DSP1618x24 contains 24K x 16 ROM. 5-4142.c Figure 2-5. DSP1618 Block Diagram DRAFT COPY Lucent Technologies Inc.
Page 35: Figure 2-6.Dsp1627 Block Diagram
DOEN2 OR PB2 sdx2(IN) saddx DOEN1 SADD2 OR PB3 sioc2 IOBIT[3:0] OR PB[7:4] saddx2 † These registers are accessible through external pins only. ‡ DSP1627x32 contains 32K x 16 internal ROM. 5-4142.d Figure 2-6. DSP1627 Block Diagram DRAFT COPY Lucent Technologies Inc.
Page 36: Figure 2-7.Dsp1628 Block Diagram
† These registers are accessible through external pins only. ‡ DSP1628x16 contains a total of 16K x 16 internal RAM, and DSP1628x08 contains a total of 8K x 16 internal RAM. Figure 2-7. DSP1628 Block Diagram DRAFT COPY Lucent Technologies Inc.
Page 37: Figure 2-8.Dsp1629 Block Diagram
IOBIT[3:0] OR PB[7:4] saddx2 † These registers are accessible through external pins only. ‡ DSP1629x16 contains 16K x 16 internal RAM, and DSP1629x10 contains 16K x 10 internal RAM. Figure 2-8. DSP1629 Block Diagram DRAFT COPY Lucent Technologies Inc.
Page 38: Device Architecture
Power Control Register PSTAT Parallel I/O Status Register Internal ROM (1 Kword for DSP1611, 24 Kwords for DSP1617, 16 Kwords for DSP1618, 24 Kwords for DSP1618x24, 36 Kwords for DSP1627, 32 Kwords for DSP1627x32, 48 Kwords for DSP1628 and DSP1629)
Page 39 Data Space Address Bus Data Space Data Bus DUAL-PORT RAM Internal dual-port RAM (12 Kwords for DSP1611, 4 Kwords for DSP1617 and DSP1618, 6 Kwords for DSP1627, 8 Kwords for DSP1628x08, 16 Kwords for DSP1628x16, 10 Kwords for DSP1629x10, and 16 Kwords for...
Page 40: Memory Space And Bank Switching
(see Section 3.2.2). IROM EROM † x = 4 for DSP1617 and DSP1618. x = 6 for DSP1627. x = 8 for DSP1628x08. x = 10 for DSP1629x10. x = 12 for DSP1611. x = 16 for DSP1628x16 and DSP1629x16.
Page 41: Internal Instruction Pipeline
The following is provided for information only. The relevant hardware is shown in Figure 2-9. X SPACE MEM. INSTRUCTIONS XAAU CONTROL DECODE YAAU DECODE 5-4143 Figure 2-9. Hardware Block Diagram for Internal Pipeline DRAFT COPY Lucent Technologies Inc. 2-13...
Page 42: Table 2-4. Single-Cycle Instruction Internal Pipeline
YAB to the RAM. Also, the DAU decoder decodes instr The decoders direct a RAM read of data to the DAU. The RAM is being accessed. The RAM places the data on the YDB, and it is loaded into the DAU. DRAFT COPY 2-14 Lucent Technologies Inc.
Page 43: Table 2-5. Two-Cycle Fetch Internal Pipeline
The data, coeff, from the X memory is transferred to the x register. The data transferred to the RAM from the y register. The data is transferred from the RAM to the y register. The RAM is written with data DRAFT COPY Lucent Technologies Inc. 2-15...
Page 44: Core Architecture Overview
(8) re (16) c1 (8) ALU/SHIFT c2 (8) auc (16) r0 (16) a0 (36) psw (16) r1 (16) a1 (36) r2 (16) ybase (16) r3 (16) EXTRACT/SAT 5-1741.a Figure 2-10. DSP1600 Core Functions DRAFT COPY 2-16 Lucent Technologies Inc.
Page 45: Y Space Address Arithmetic Unit (Yaau)
RAM and three external data memory segments (ERAMHI, ERAMLO, and IO). One individual address in the IO memory segment also has an individually decoded output DSEL facilitating glueless memory- mapped I/O. 1.Not available in the DSP1627/28/29. DRAFT COPY Lucent Technologies Inc. 2-17...
Page 46: Space Address Arithmetic Unit (Xaau)
1.The internal ROM memory of the DSP1611 is only available with a standard boot routine. DSP1611 devices do not offer the secure mask option. DRAFT COPY 2-18 Lucent Technologies Inc.
Page 47: Internal Memories
RAM space. The DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 all feature large, mask- programmable internal ROM memories that can be encoded with programs, fixed data, or both. The DSP1617 ROM contains 24 Kwords, the DSP1618 ROM contains 16 Kwords, the DSP1618x24 ROM contains 24 Kwords, the DSP1627 ROM contains 36 Kwords, the DSP1627x32 ROM contains 32 Kwords, the DSP1628 contains 48 Kwords, and the DSP1629 contains 48 Kwords.
Page 48: Bit Manipulation Unit (Bmu)
1.XX denotes the last two digits of the device name, e.g., XX = 11 for the DSP1611. DRAFT COPY 2-20 Lucent Technologies Inc.
Page 49: Parallel Input/Output (Pio) (Dsp1617 Only)
2.7 Parallel Input/Output (PIO) (DSP1617 Only) The DSP1617 has an 8-bit parallel I/O interface for rapid transfer of data with external devices such as other DSPs, microprocessors, or peripheral I/O devices. Minimal or no additional logic is required to interface with peripheral devices, and data rates of up to 20 Mbytes/s are obtained at an instruction cycle of 25 ns.
Page 50: Bit Input/Output (Bio)
The value in the timer can be read on-the-fly by a data move from timer0. The value written to timer0 is also stored in the period register and held as the count that the timer will return to if in the repeating mode. DRAFT COPY 2-22 Lucent Technologies Inc.
Page 51: Hardware Development System (Hds) Module
I/O units. The STOP pin controls the internal processor clock. The various power management options can be chosen based on power consumption, wake-up latency require- ments, or both. Power management is fully described in Section 3.6, Power Management. DRAFT COPY Lucent Technologies Inc. 2-23...
Page 52: Software Architecture
Chapter 3 Software Architecture...
Page 53 3.4.5 Trap Description ........................3-38 3.4.6 Powerdown with the AWAIT State ..................3-40 3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) ..........3-42 3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) ........3-44 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only) ............3-47 3.5.1 PLL Control Signals ......................3-48 3.5.2...
Page 54: Register View Of The Dsp1611/17/18/27/28/29
Section 3.4, Interrupts, dis- cusses both the vectored interrupts and the DSP16A compatible interrupts. (The DSP16A compatible interrupts are available on the DSP1617 only.) Section 3.5, Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only), describes the DSP1627/28/29’s phase-lock loop based clock synthesizer. And finally, the flexible power manage- ment features are discussed in Section 3.6, Power...
Page 55: Table 3-2. Program-Accessible Registers By Type, Listed Alphabetically
PHIF control register (DSP1611/18/27/28/29) c & s PHIF Program interrupt return address XAAU Note: Registers sioc, sioc2, srta, srta2, tdms, and tdms2 are not readable. Alternate accumulators aa0 and aa1 are only accessible with the BMU swap instruction. DRAFT COPY Lucent Technologies Inc.
Page 56 (continued) 3.1.1 Types of Registers (continued) Table 3-2. Program-Accessible Registers by Type, Listed Alphabetically (continued) Register Name Description Type Section pioc PIO control register (DSP1617 only) c & s pllc Control registers for clock synthesizer control Clock (DSP1627/28/29 only) Synthesizer...
Page 57: Figure 3-1.Program-Accessible Registers, Dsp1611/17/18/27/28/29
XAAU CACHE & YAAU CONTROL cloop ybase PHIF pdx0(IN) pdx0(OUT) phifc (DSP1611/18/27/28/29 ONLY) pdx<0—7>(IN) ECCP (DSP1618/28 ONLY) pdx<0—7>(OUT) CLOCK SYNTHESIZER pioc (DSP1617 ONLY) pllc powerc (DSP1627/28/29 ONLY) SIO2 TIMER tdms tdm2 timerc saddx2 sioc2 saddx sioc timer0 srta2 sdx2 srta CONTROL &...
Page 58: Register Length Definition
16-bit, except 32-bit to accumulators in special function instruction 32-bit, except 16-bit in p = x * y Note: The user must specify h or l in the ALU immediate, e.g., aD = aS<h,l> OP IM16. p or y is sign-extended to 36 bits for operations with accumulators. DRAFT COPY Lucent Technologies Inc.
Page 59: Register Reset Values
•••••••••••••••• SSSSSSSSSSSSSSSS † DSP1617 only. 0111010011000010. ‡ DSP1617 value is § If EXM is high and INT1 is low and RSTB goes high, mwait will contain all ones instead of all zeros. †† DSP1627/28/29 only. ‡‡ DSP1618/28 only. §§ DSP1611/18/27/28/29 only.
Page 60: Flags
The random bit is generated by a 10-stage pseudorandom sequence generator (PSG) that is updated after either a heads or tails test. (See Section 5.1.6, DAU Pseudorandom Sequence Generator (PSG) for more details.) § These flags are only set after an appropriate write to the BIO port (cbit register). DRAFT COPY Lucent Technologies Inc.
Page 61: Memory Space And Addressing
RAM banks. OFF-CHIP EXTERNAL MEMORY ADDRESS BUS YAAU INTERNAL EXTERNAL EXTERNAL EXTERNAL DUAL-PORT ERAMHI ERAMLO YDB DATA BUS EXTERNAL MEMORY DATA BUS 5-4110 Figure 3-2. Data (Y) Memory Space DRAFT COPY Lucent Technologies Inc.
Page 62: Table 3-7. Data Memory Map (Y-Memory Space)
April 1998 Software Architecture 3.2 Memory Space and Addressing (continued) 3.2.1 Y-Memory Space (continued) Table 3-7. Data Memory Map (Y-Memory Space) Decimal Hexadecimal Address DSP1611 DSP1617/1618 DSP1627 DSP1628 DSP1628 DSP1629 DSP1629 Address in r0, r1, r2, r3 0x0000 RAM1 RAM1...
Page 63: X-Memory Space
MAP 1—4 corresponds to the value of EXM and LOWPR. OFF-CHIP XAB ADDRESS BUS XAAU EXTERNAL MEMORY ADDRESS BUS INTERNAL INTERNAL EXTERNAL DUAL-PORT EROM EXTERNAL MEMORY DATA BUS XDB DATA BUS 5-4111 Figure 3-3. Instruction/Coefficient (X) Memory Space DRAFT COPY 3-10 Lucent Technologies Inc.
Page 64: Table 3-8. Dsp1611 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 65: Table 3-9. Dsp1617 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 66: Table 3-11. Dsp1618X24 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 67: Table 3-12. Dsp1627 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 68: Table 3-13. Dsp1627X32 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 69: Table 3-14. Dsp1628X08 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 70: Table 3-15. Dsp1628X16 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 71: Table 3-16. Dsp1629X10 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 72: Table 3-17. Dsp1629X16 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 73: Table 3-18. Interrupts In X-Memory Space
0x24 Reserved 0x28 0x2c 0x30 PIBF/PIDS 0x34 POBE/PODS 0x38 JINT 0x42 TRAP from user 0x46 † DSP1617 only. ‡ The icall instruction is reserved for use by the hardware development system. § DSP1618/28 only. DRAFT COPY 3-20 Lucent Technologies Inc.
Page 74: Arithmetic And Precision
For example: a0=0 auc=0x80 enable X=Y= r1=table y=*r1++ square, and load both y and x do 100 { a0=a0+p p=x*y y=*r1++ accumulate, square, and load both y and x auc=0 disable X=Y= DRAFT COPY Lucent Technologies Inc. 3-21...
Page 75: Table 3-19. Arithmetic Unit Control (Auc) Register
† The auc is a 16-bit register of which 9 bits [8:0] are used for control. The unused upper 7 bits [15:9] are always zero when read and should always be written with zeros to make the program compatible with future chip versions. The auc register is cleared at reset. DRAFT COPY 3-22 Lucent Technologies Inc.
Page 76 35—32. This mode is most often used if both x and y operands are 16-bit integers. x(16) y(32) p(32) a0, a1(36) 5-4112 Figure 3-4. p Register to Accumulator Bit Alignment, auc[1:0] = 00 DRAFT COPY Lucent Technologies Inc. 3-23...
Page 77 LSBs of the product can be tolerated. x(16) y(32) p(32) a0, a1(36) 5-4113 Figure 3-5. p Register to Accumulator Bit Alignment, auc[1:0] = 01 DRAFT COPY 3-24 Lucent Technologies Inc.
Page 78 Note: The top 2 magnitude bits are shifted into overflow bits 33 and 32 that can only be read via the psw register, and saturation can be detected if enabled in the auc register. x(16) y(32) p(32) a0, a1(36) 5-4114 Figure 3-6. p Register to Accumulator Bit Alignment, auc[1:0] = 10 DRAFT COPY Lucent Technologies Inc. 3-25...
Page 79 Note: The top magnitude bit is shifted into overflow bit 32 that can only be read via the psw register, and saturation can be detected if enabled in the auc register. x(16) y(32) p(32) a0, a1(36) 5-4114.a Figure 3-7. Register to Accumulator Bit Alignment, auc[1:0] = 11 DRAFT COPY 3-26 Lucent Technologies Inc.
Page 80: Interrupts
(HDS) to gain control of the processor. In the DSP1617, a set of interrupts have been retained to maintain compatibility with the DSP16A. Four I/O inter- rupts and the hardware interrupt pin (INT0) from DSP16A can be used in a DSP16A-compatible mode (see Section 3.4.7, Interrupts in DSP16A-Compatible Mode (DSP1617...
Page 81: Figure 3-8.Interrupt Operation
Figure 3-8 is a functional block diagram of the interrupt hardware. CLEAR BITS 4—8,11 ONLY INC REGISTER INS REGISTER MASKS CLEARS TRAP INTERRUPT icall IACK PROCESSING HDS trap VEC[3:0] 5-4115b Figure 3-8. Interrupt Operation DRAFT COPY 3-28 Lucent Technologies Inc.
Page 82: Interrupt Sources
Hardware or software: The icall instruction generates a software interrupt; the rest are generated by hardware. DSP16A—Compatible (DSP1617 only) or not: Four of the interrupt sources (PIDS, PODS, OBE, and IBF) have a different effect depending on whether they are enabled from the pioc (DSP16A compatibility mode) or enabled from the inc register.
Page 83: Figure 3-9.Dsp16A-Compatible Interrupts (Dsp1617 Only)
Information Manual Software Architecture April 1998 3.4 Interrupts (continued) 3.4.2 Interrupt Sources (continued) FROM CHIP PIN INTERRUPTS pioc ENABLED MASKS icall IACK INTERRUPT PROCESSING TO CHIP PIN 5-4146 Figure 3-9. DSP16A-Compatible Interrupts (DSP1617 Only) DRAFT COPY 3-30 Lucent Technologies Inc.
Page 84: Outputs Of Interrupts
† Pins VEC[3:0] are multiplexed with pins IOBIT[7:4]. Bit 12 of the ioc register must be cleared to enable VEC[3:0]. ‡ The icall instruction is reserved for use by the hardware development system. § Available on DSP1617 only. †† DSP1618/28 only.
Page 85: Interrupt Operation
PC register. At time frame F, the next instruction begins. Code Fragment INT1 Interrupt Service Routine • • • int1_isr: a0=0x0 a0=*r0 //r0 points to ERAMHI mwait=0x0 2*nop r0=ERAM_HI ireturn inc=0x20 • • Single cycle interruptible instructions • DRAFT COPY 3-32 Lucent Technologies Inc.
Page 86: Figure 3-10.Timing Diagram Of A Simple Interrupt
D. Start executing instructions in interrupt service routine. E. ireturn instruction is executed; end of interrupt service routine. F. Next instruction. Figure 3-10. Timing Diagram of a Simple Interrupt (Asserted During an Interruptible Instruction and No Other Pending Interrupts) DRAFT COPY Lucent Technologies Inc. 3-33...
Page 87 † A zero in any bit of the inc register disables the corresponding interrupt, and a one in any bit enables the corresponding interrupt. ‡ JINT is a JTAG interrupt and is controlled by the HDS. It can be made unmaskable by the Lucent Technologies development system tools.
Page 88: Figure 3-11.Interrupt Disable Latency
† A zero in any bit of the ins register disables the corresponding interrupt, and a one in any bit enables the corresponding interrupt. ‡ JINT is a JTAG interrupt and is controlled by the HDS. It can be made unmaskable by the Lucent Technologies development system tools.
Page 89: Figure 3-12.Interrupt Request Circuit Diagram
3.4.4 Interrupt Operation (continued) Concurrent Interrupts If using DSP16A-compatible interrupts in the DSP1617 device, concurrent interrupts must be handled with extra care in order to guarantee that all interrupts will be serviced (details are described in Section 4.2.6 of the DSP16A Information Manual ).
Page 90: Figure 3-13.Timing Diagram Of Concurrent Interrupts
G. Branch to interrupt service routine caused by second INT1. H. Start executing instructions in interrupt service routine. Figure 3-13. Timing Diagram of Concurrent Interrupts (Interrupt Is Asserted During the Service of the Same Interrupt.) DRAFT COPY Lucent Technologies Inc. 3-37...
Page 91: Trap Description
*r0=sdx /* move serial input data into RAM Note: pioc bits 9, 8 = 0 to disable ibf and obe interrupts in DSP16A-compatible mode (DSP1617 only). 3.4.5 Trap Description The maximum interrupt latency in a program can be as long as thousands of cycles if a cache loop uses a large repeat count.
Page 92: Figure 3-14.Timing Diagram Of User Trap
C. Branch to trap service routine. D. Start executing instructions in trap service routine. E. ireturn instruction is executed; end of trap service routine. F. Next interruptible instruction. Figure 3-14. Timing Diagram of User Trap DRAFT COPY Lucent Technologies Inc. 3-39...
Page 93: Powerdown With The Await State
D. Executing one more instruction (nop) after coming out of sleep mode. E. Branching to interrupt service routine. F. Start executing instructions in interrupt service routine. Figure 3-15. Timing Diagram of Entering and Exiting Powerdown Mode DRAFT COPY 3-40 Lucent Technologies Inc.
Page 94 Code Example for Sleep Mode (assuming execution from internal RAM) sleep: alf=0x8000 set bit 15 of alf register one more instruction executed sleep here external interrupt occurs one more instruction executed branch here return here main code: DRAFT COPY Lucent Technologies Inc. 3-41...
Page 95: Interrupts In Dsp16A-Compatible Mode (Dsp1617 Only)
0x10 to the ins register before issuing ireturn. One notable timing difference is the IACK signal that is asserted at the rising edge of the CKO clock in the DSP1617 instead of the falling edge of CKO as in DSP16A.
Page 96 Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Software Architecture 3.4 Interrupts (continued) 3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) (continued) sioint: service internal (IBF) interrupt a1=sdx reading sdx clears IBF pdx0=a1 DUMMY CODE ireturn start: pioc=0x1a20 enable IBF and INT0 interrupts...
Page 97: Timing Examples, Dsp16A-Compatible Mode (Dsp1617 Only)
Software Architecture April 1998 3.4 Interrupts (continued) 3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) Concurrent Internal and External Interrupts—Figure 3-16 shows the timing sequence of concurrent IBF and INT0 interrupts with both interrupt signals synchronized to the falling edge of the CKO clock. Four cases are given for different INT0 signals asserted at the same time as, or after, the IBF signal.
Page 98: Figure 3-17.Timing Sequences Of Concurrent Internal And External Interrupts, Dsp16A Compatible Mode
April 1998 Software Architecture 3.4 Interrupts (continued) 3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) (continued) Concurrent Internal and External Interrupts—Figure 3-17 also shows the timing sequence of concurrent IBF and INT0 interrupts with three cases of IBF asserted after the INT0 signal.
Page 99: Figure 3-18.Timing Sequence Of Concurrent External Interrupts, Dsp16A Compatible Mode
Software Architecture April 1998 3.4 Interrupts (continued) 3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) (continued) Concurrent External Interrupts—Figure 3-18 shows the timing sequence of concurrent INT0 interrupts. Case 1—INT0 signal is negated at point B and asserted again at point C. Because the previous INT0 is still pending, the new INT0 must be asserted until the second rising edge of IACK.
Page 100: Clock Synthesis (Dsp1627, Dsp1628, And Dsp1629 Only)
Signals shown in bold are control bits from the pllc register or the powerc register. If PLLSEL = 0, DSP runs from the 1X version of CKI input clock. Other signals from the powerc register also control the clock source. Figure 3-19. Clock Source Block Diagram DRAFT COPY Lucent Technologies Inc. 3-47...
Page 101: Pll Control Signals
Otherwise, the LOCK flag is not reset, and there might be no way to determine if the PLL is stable when the input clock is applied again. The lock-in time depends on the operating frequency and the values programmed for M and N (see Table 3-27). DRAFT COPY 3-48 Lucent Technologies Inc.
Page 102 The PLL can be deselected and powered down in the same instruction by clearing bits PLLEN and PLLSEL of the pllc register; all remaining pllc bits must remain unchanged. Do not remove the input clock (CKI) before the PLL is powered down. DRAFT COPY Lucent Technologies Inc. 3-49...
Page 103: Pll Programming Examples
Table 3-25. Latency Times for Switching Between CKI and PLL-Based Clocks Minimum Maximum Latency (cycles) Latency (cycles) Switch to PLL-based clock N + 2 Switch from PLL-based clock M/N + 1 M + M/N + 1 DRAFT COPY 3-50 Lucent Technologies Inc.
Page 104: Table 3-26. Phase-Locked Loop Control (Pllc) Register
The DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the PLL is locking. Completion of the lock-in interval is indicated by assertion of the LOCK flag. DRAFT COPY Lucent Technologies Inc. 3-51...
Page 105: Power Management
SIO2DIS: This bit powers down the SIO2 in the same way SIO1DIS powers down the SIO1. PIODIS (DSP1617 only): This is a powerdown signal to the PIO I/O unit. It disables the clock input to the unit eliminating any sleep power associated with the PIO. Because the gating of the clocks can result in incomplete transactions, it is recommended that this option be used in applications where the PIO is not used or if reset can be used to reenable the PIO unit.
Page 106: Table 3-28. Powerc Fields (Dsp1617)
1 = INT1 clears NOCK field. SIO1DIS 1 = disable SIO1. SIO2DIS 1 = disable SIO2. PIODIS 1 = disable PIO (DSP1617 only). PHIFDIS 1 = disable PHIF (DSP1611/18/27/28/29 only) TIMERDIS 1 = disable timer. ECCPDIS 1 = disable ECCP (DSP1618/28 only)
Page 107: Figure 3-20.Power Management Using The Powerc Register (Dsp1611/17/18 Only)
If the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered down. Figure 3-20. Power Management Using the powerc Register (DSP1611/17/18 Only) DRAFT COPY 3-54 Lucent Technologies Inc.
Page 108: Figure 3-21.Power Management Using The Powerc Register (Dsp1627/28/29 Only)
If the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered down. PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc. Figure 3-21. Power Management Using the powerc Register (DSP1627/28/29 Only) DRAFT COPY Lucent Technologies Inc. 3-55...
Page 109: Stop Pin
AWAIT bit cannot be set. If executing code with two or more wait-states, it is recommended that the alf register be set from within the cache to prevent any pending interrupt from being ser- viced until after the DSP enters the AWAIT state. DRAFT COPY 3-56 Lucent Technologies Inc.
Page 110: Power Management Sequencing
For devices with the PLL and slow clock ring oscillator option, the use of the internal ring oscillator (slow clock) is required if entering the low-power state. For reliable operation in all environments, the ring oscillator must be selected as the clock source before the PLL is turned off. DRAFT COPY Lucent Technologies Inc. 3-57...
Page 111: Power Management Examples
User code executes here powerc=0x00F0 Select high-speed clock 2*nop Wait for it to take effect powerc=0x0000 Turn peripheral units back on 1.In this case, the wake-up latency is determined by the period of the ring oscillator clock. DRAFT COPY 3-58 Lucent Technologies Inc.
Page 112 Wait for it to take effect ins=0x0010 Clear the INT0 status bit 1.In this case, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. xltwait is a called subroutine that waits for stabilization. DRAFT COPY Lucent Technologies Inc. 3-59...
Page 113 Stop internal processor clock, interrupt circuits*/ active Needed for bedtime execution. Only sleep power plus PLL power consumed here... Interrupt wakes up the device. next: . . . User code executes here powerc=0x0000 Turn peripheral units back on DRAFT COPY 3-60 Lucent Technologies Inc.
Page 114 Enable PLL, continue to run off slow clock call pllwait Loop to check for LOCK flag assertion next: powerc=0x00F0 Select high-speed PLL based clock 2*nop Wait for it to take effect powerc=0x0000 Turn the peripheral units back on DRAFT COPY Lucent Technologies Inc. 3-61...
Page 115 Loop if the bit is not set ins=0x0100 Clear the TIME interrupt bit return Return to the main program An example subroutine for pllwait follows: pllwait: if lock return wait for lock flag to be set goto pllwait DRAFT COPY 3-62 Lucent Technologies Inc.
Page 116: Instruction Set
Chapter 4 Instruction Set...
Page 117 CHAPTER 4. INSTRUCTION SET CONTENTS 4 Instruction Set ..............................4-1 Notation .............................4-2 Instruction Cycle Timing ........................4-2 Addressing Modes ..........................4-3 4.3.1 Register Indirect Addressing ....................4-3 4.3.2 Compound Addressing .......................4-5 4.3.3 Direct Data Addressing .......................4-7 Processor Flags ..........................4-9 Instruction Set..........................4-11 4.5.1 Control Instructions ......................4-12 4.5.2 Cache Instructions ......................4-14 4.5.3...
Page 118 April 1998 4 Instruction Set All DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 instructions are 16 bits wide and resemble C code. The instructions are grouped into seven categories: Control instructions direct program flow and can be conditionally executed on the basis of the state of internal flags.
Page 119: Notation
For the DSP1611/17/18/27/28/29, the instruction cycle is defined as the execution time of a single-cycle instruction in the absence of wait-states. For a 60 MHz 2x CKI or a 30 MHz 1x CKI, the instruction cycle is 33 ns. For the DRAFT COPY Lucent Technologies Inc.
Page 120: Addressing Modes
(upper half) to the memory location in r0. In both cases, the register r0 or pt is said to point to the data in memory because the register contains a 16-bit address for a memory read or write. DRAFT COPY Lucent Technologies Inc.
Page 121 Modulo addressing works only with *rM++, *rMpz, and *rMzp. Section 5.3, Y Address Arithmetic Unit (YAAU) has more detail on modulo addressing. DRAFT COPY Lucent Technologies Inc.
Page 122: Compound Addressing
(e.g., r1pz : r1). The two alphanumerics in mnemonics zp, pz, m2, and jk stand for the postin- crements after Step 2 and Step 3. z is zero, p is plus 1, m is minus 1, 2 is plus 2, and j and k are increments from the j and k registers. DRAFT COPY Lucent Technologies Inc.
Page 123: Figure 4-1.Compound Addressing
*rMjk : R † NEXT ADDRESS IN rM TEMP *(rM + j) † FINAL ADDRESS IN rM *((rM + j) + k) 5-4148 † j or k can be positive or negative. Figure 4-1. Compound Addressing DRAFT COPY Lucent Technologies Inc.
Page 124: Direct Data Addressing
The register DR, specified in the opcode by bits 6—9, can be one of a set of 16. They are listed as follows. Table 4-2. Direct Data Addressing Register DR Field Register DR Field 0000 1000 0001 1001 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 DRAFT COPY Lucent Technologies Inc.
Page 125: Figure 4-2.Direct Data Addressing
/* Offset=0x15; Store (1 0101) into lower 5 bits of ybase Address in ybase is 0x1215, demonstrated below: 0001 0010 001 = upper 11 bits 1 0101 = lower 5 bits 0001 0010 0011 0101 = address=0x1235 Store 0xface (contents of a0) into location 0x1235. DRAFT COPY Lucent Technologies Inc.
Page 126: Processor Flags
Mathematical Overflow (32-bit Overflow)—LMV is true if bit 31 of the accumulator differs from any of the guard bits (32—35) after the last DAU or BMU operation. This indicates a number not representable in 32 bits. DRAFT COPY Lucent Technologies Inc.
Page 127: Instruction Set
(For further information, see Section 5.1.6, DAU Pseudorandom Sequence Generator (PSG).) § These flags are only set after an appropriate write to the BIO port (cbit register). †† DSP1627/28/29 only. ‡‡ DSP1618/28 only. DRAFT COPY 4-10 Lucent Technologies Inc.
Page 128 = extracts (aS, arM) aD = extractz (aS, arM) aD = extracts (aS, IM16) aD = extractz (aS, IM16) aD = insert (aS, arM) aD = insert (aS, IM16) aD = aS : aaT DRAFT COPY Lucent Technologies Inc. 4-11...
Page 129: Control Instructions
4 Kword memory section. 3-bit value in B-field instruction B selects one of return (same as goto pr) ireturn (same as goto pi) goto pt call pt † DSP1627/28/29 only. ‡ DSP1618/28 only. DRAFT COPY 4-12 Lucent Technologies Inc.
Page 130 (or ireturn) must be a load of the pi register; otherwise, the goto pi (or ireturn) instruction will not exe- cute properly. DRAFT COPY Lucent Technologies Inc. 4-13...
Page 131: Cache Instructions
† The assembly-language statements (do cloop and redo cloop) are used to specify that the number of iterations is to be taken from the cloop register. K is set to 0 in the instruction encoding to select cloop. DRAFT COPY 4-14 Lucent Technologies Inc.
Page 132: Data Move Instructions
YAAU registers in the DSP, unsigned registers are zero-extended from 9 bits to 16 bits. Signed registers j and k are sign-extended from 9 bits to 16 bits. DRAFT COPY Lucent Technologies Inc. 4-15...
Page 133: Table 4-9. Replacement Table For Data Move Instructions
Serial protocol register, port 2. pioc Parallel I/O control register (DSP1617 only). pdx<0—7> Parallel I/O data registers (pdx0 only in DSP1611/18/27/28/29). † Data moves to y, a0, or a1 load the high half (bits 31—16) of the register. If clearing of the destination is enabled according to the CLR field of the auc register, the low half of the destination register is cleared (0) when the high half is loaded.
Page 134 PC prior to the interrupt. Writes to pi do not alter its contents for less than one instruction cycle after shadowing resumes except during interrupt service routines. § sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable. DRAFT COPY Lucent Technologies Inc. 4-17...
Page 135 R = *rM. This combination is used for stack operations. The pointer register rM is decremented, and data is writ- ten from the new memory location to the register R. The decrement instruction is not interruptible, so interrupts cannot corrupt the two-instruction pop sequence. DRAFT COPY 4-18 Lucent Technologies Inc.
Page 136: Special Function Group
Normally, a test of c0, such as if c0lt goto 0x400, increments c0. In the case of the ifc c0lt F2 instruction, c0 is not incremented. Special Function Instructions if CON F2 ifc CON F2 DRAFT COPY Lucent Technologies Inc. 4-19...
Page 137: Table 4-10. Special Function Statements
Table 4-3 for definitions of pro- c1ge, c1lt, heads, tails, true, false, allt, allf, somet, cessor flags. somef, oddp, evenp, mns1, nmns1, npint, njint, † ‡ lock , ebusy † DSP1627/28/29 only. ‡ DSP1618/28 only. DRAFT COPY 4-20 Lucent Technologies Inc.
Page 138 ALIGN field of the auc register. aD = ~aS The contents of the source accumulator (aS) are inverted and placed in the destination accumulator—aD (one's complement). DRAFT COPY Lucent Technologies Inc. 4-21...
Page 139: Multiply/Alu Group
In this example, the data in the Y source is copied into the y register in line 1. In line 2, the logical AND of the data in the source accumulator (aS) and the data in y as a result of line 1 are calculated. The result is loaded into the destination accumulator. DRAFT COPY 4-22 Lucent Technologies Inc.
Page 140: Table 4-12. Multiply/Alu Instructions
§ The l in [ ] is an optional argument that specifies the low 16 bits of aT or y. Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corresponding CLR bit in the auc register is zero. auc is cleared by reset. DRAFT COPY Lucent Technologies Inc. 4-23...
Page 141: Table 4-13. Replacement Table For Multiply/Alu Instructions
If the X=Y= bit is set and the hardware development system is used, breakpoints or single-stepping will corrupt the x register. It is best to set the X=Y= bit just before the single-cycle routine is used and clear it just after. DRAFT COPY 4-24 Lucent Technologies Inc.
Page 142: Table 4-14. Instruction For Loading The X And Y Registers Into The Squaring Mode
(aD). The bit alignment between p and aS is a function of the ALIGN field of the auc register. aD = y The contents of the y register are copied into the destination accumulator (aD). DRAFT COPY Lucent Technologies Inc. 4-25...
Page 143 Y = aTl The data in the low half (bits 15—0) of the specified accumulator is written into the specified Y destina- tion. If saturation on overflow is selected by using the SAT field of the auc register, the transferred accumulator value is limited. (See Section 5.1, Data Arithmetic Unit.) DRAFT COPY 4-26 Lucent Technologies Inc.
Page 144 Z destination. The data in the high half of the accumulator is not altered. (See Figure 4-3, on page 4-28.) DRAFT COPY Lucent Technologies Inc. 4-27...
Page 145: Figure 4-3.Compound Addressing With Accumulators Or Y Register
Only one of the four possible postmodification conditions is shown: *rMpz. The others are the same as in Sec- tion 4.3.2, Compound Addressing. DRAFT COPY 4-28 Lucent Technologies Inc.
Page 146: F3 Alu Instructions
36-bit addition. – 36-bit subtract. & 36-bit bitwise AND. 36-bit bitwise OR. 36-bit bitwise exclusive OR. IM16 immediate 16-bit data, sign-, zero-, or one-extended as appropriate. DRAFT COPY Lucent Technologies Inc. 4-29...
Page 147: Bmu Instructions
Logical right shift (32-bit shift, 0s filled in). <<< Logical left shift (36-bit shift, 0s filled in). ar<0—3> One of the four auxiliary BMU registers. IM16 16-bit value Immediate data. aa0, aa1 One of the alternate accumulators. DRAFT COPY 4-30 Lucent Technologies Inc.
Page 148: Figure 4-4.Bmu Shifting Operations
LOGICAL LEFT SHIFT AND ARITHMETIC LEFT SHIFT 32 31 16 15 AFTER 0---------0 32 31 16 15 BEFORE ARITHMETIC RIGHT SHIFT 35 32 31 16 15 s---------------s AFTER 5-4151 Figure 4-4. BMU Shifting Operations DRAFT COPY Lucent Technologies Inc. 4-31...
Page 149: Figure 4-5.Extraction
(in bits), and the lower 8 bits of IM16 hold the OFFSET from bit 0 of aS (in bits). Flags are set based on the value written to aD. WIDTH OFFSET SPECIFIED IN IMMEDIATE OR arM SOURCE ACCUMULATOR ZERO EXTENDED OR DESTINATION SIGN EXTENDED ACCUMULATOR 5-4152 Figure 4-5. Extraction DRAFT COPY 4-32 Lucent Technologies Inc.
Page 150: Figure 4-6.Case 1. Source As And Destination Accumulators Different
Figure 4-6. Case 1. Source aS and Destination Accumulators Different BEFORE aS = aD WIDTH SOURCE & DESTINATION ACCUMULATOR OFFSET AFTER SOURCE 2 5-4154 Figure 4-7. Case 2. Source aS and aD Destination Accumulators the Same DRAFT COPY Lucent Technologies Inc. 4-33...
Page 151: Figure 4-8.Shuffle Instruction
Odd Parity—True if bits 35—0 have an odd number of ones (zeros). mns1 Minus 1—True if all bits 35—0 are ones (minus 1 in two's complement). nmns1 Not Minus 1—True for all other patterns than all ones. DRAFT COPY 4-34 Lucent Technologies Inc.
Page 152: Assembler Ambiguities
If the user does not provide one of these key words for an instruction that is open to more than one interpretation, the assembler chooses the encoding based on the above priority. DRAFT COPY Lucent Technologies Inc. 4-35...
Page 153: Table 4-18. Summary Of Ambiguous Dsp1600 Commands Requiring A Mnemonic
= a0 or a1. aT = a0, a1, a0l, or a1l. Z = *rMzp, *rMpz, *rMm2, or *rM++j (M = 0, 1, 2, or 3). rM = r0, r1, r2, or r3. DRAFT COPY 4-36 Lucent Technologies Inc.
Page 154: Core Architecture
Chapter 5 Core Architecture...
Page 155 CHAPTER 5. CORE ARCHITECTURE CONTENTS 5 Core Architecture ............................5-1 Data Arithmetic Unit...........................5-1 5.1.1 Inputs and Outputs ......................5-2 5.1.2 Multiplier Functions ......................5-2 5.1.3 ALU .............................5-2 5.1.4 Accumulators ........................5-3 5.1.5 Counters ..........................5-4 5.1.6 DAU Pseudorandom Sequence Generator (PSG) ..............5-7 5.1.7 Control Registers ........................5-9 X Address Arithmetic Unit (XAAU) ....................5-11 5.2.1 Inputs and Outputs ......................5-11...
Page 156: Data Arithmetic Unit
16 x 16 MULTIPLY p (32) SHIFT (–2, 0, 1, 2) ALU/SHIFT FLAGS c0 (8) a0 (36) c1 (8) a1 (36) c2 (8) auc (16) FLAGS EXTRACT/SAT. psw (16) 5-4156.a Figure 5-1. DAU—Data Arithmetic Unit DRAFT COPY Lucent Technologies Inc.
Page 157: Inputs And Outputs
Unit) provides more complex accumulator functions. The instruction groups using the ALU are as follows: Special function instructions (F2); see Table 4-11. Multiply/ALU instructions; see Table 4-12. ALU instructions (F3); see Table 4-15. DRAFT COPY Lucent Technologies Inc.
Page 158: Accumulators
If clearing of the low half of the register is disabled, the two register loads can be performed in either order. A write to the high half of the p register has no effect on the low half, there is no option that allows clearing the low half when the high half is written. DRAFT COPY Lucent Technologies Inc.
Page 159: Counters
← cN + 1 cN ← cN + 1 cN ← cN + 1 if cNge Instruction if cNlt Instruction N = 0 or 1 N = 0 or 1 Figure 5-2. Conditional Instructions Using Counter Conditionals DRAFT COPY Lucent Technologies Inc.
Page 160 No instructions increment c2 because its only use is as a holding register for c1. 1.See Section 4.5.4 for a description of the special function instruction group. 2.CON is any conditional (see Section 4.5.1). DRAFT COPY Lucent Technologies Inc.
Page 161: Figure 5-3.The Ifc Con F2 Instruction
Copies the value of c1 into c2 whenever an instruction of the form † ifc CON F2_Instruction executes and the condition CON is true † CON is any conditional (see Section 4.5.1) Section 4.5.4 for a description of the special function (F2) instruction group. DRAFT COPY Lucent Technologies Inc.
Page 162: Dau Pseudorandom Sequence Generator (Psg)
/* enable reset of PSG pi=label /* reset PSG, write pi register with address of /* next instruction in case interrupt occurs here label:nop /* nop is needed here auc=0x100 /* disable reset of PSG DRAFT COPY Lucent Technologies Inc.
Page 163: Figure 5-4.Dau Pseudorandom Sequence Generator
‡ The PSG is set to all ones whenever the pi register is written outside of an interrupt service routine unless the RAND bit of the auc register is set. Figure 5-4. DAU Pseudorandom Sequence Generator DRAFT COPY Lucent Technologies Inc.
Page 164: Control Registers
DAU/BMU operation produces a negative number as determined by accumulator bit 35. If bit 35 equals one, the result is negative; but if bit 35 equals zero, the result is positive. DRAFT COPY Lucent Technologies Inc.
Page 165: Table 5-4. Processor Status Word (Psw) Register
† W indicates that the bit can be read or written. ‡ All DAU flags can be read from the psw register. The DAU flags are defined in section 3.1.4 , on page 3-7. DRAFT COPY 5-10 Lucent Technologies Inc.
Page 166: Address Arithmetic Unit (Xaau)
1 Kwords each. Each bank has an enable line from the XAAU. The enable lines are enabled one at a time depending on the address and the memory map. 1.The upper case denotes that this register is not accessible by instructions. DRAFT COPY Lucent Technologies Inc. 5-11...
Page 167: Register Descriptions
For the shadow register to be modified by a data move write to the pi register, the data move must occur prior to one instruction before the first breakpoint address in an ISR. DRAFT COPY 5-12 Lucent Technologies Inc.
Page 168: Inputs And Outputs
. All of the registers are read or written through the bidirectional data bus IDB. IDB also provides the interface for loading immediate addresses into the registers. 1.DSEL not available in the DSP1627/28/29. DRAFT COPY Lucent Technologies Inc. 5-13...
Page 169: Y-Memory Space
Virtual-shift addressing is nor- mally disabled and is enabled by writing a nonzero value to re. re is cleared on reset. The following sections describe direct data addressing and virtual-shift addressing in further detail. DRAFT COPY 5-14 Lucent Technologies Inc.
Page 170: Figure 5-7.Direct Data Addressing
INSTRUCTION iN X-MEMORY T-FIELD OFFSET DR SPECIFIED SPACE DR = *(OFFSET) *(OFFSET) = DR OFFSET CONTROL ybase REGISTER BASE IN YAAU REGISTER DR 5-4160 Figure 5-7. Direct Data Addressing DRAFT COPY Lucent Technologies Inc. 5-15...
Page 171: Figure 5-8.Use Of The Rb And Re Registers
Xn – 5, Xn – 4, Xn – 3, . . . , Xn + 1 Xn – 4, Xn – 3, . . . , Xn + 2 5-4125 Figure 5-8. Use of the rb and re Registers 1.Modulo addressing works only with *rM++, *rMpz, or *rMzp. DRAFT COPY 5-16 Lucent Technologies Inc.
Page 172: Cache And Control
ROM locations than in-line coding of the same routine. For multiply/ALU instructions that require two reads to dual-port RAM, executing from the cache decreases the execution time from two instruction cycles to one instruction cycle resulting in an increase in throughput. DRAFT COPY Lucent Technologies Inc. 5-17...
Page 173: Table 5-5. Replacement Table For Cache Instruction Encoding
Cache loops cannot be interrupted. Instructions that cannot be used in the cache are the control group instructions and any instructions that contain an immediate value as the second word of a two-word instruction. DRAFT COPY 5-18 Lucent Technologies Inc.
Page 174: Control
Field JINT rsrvd EOVF EREADY rsrvd OBE2 IBF2 TIMEOUT rsrvd INT[1:0] PIBF POBE OBE IBF Table 5-10. Interrupt Status (ins) Register (DSP1618/28) 7—6 5—4 Field JINT rsrvd EOVF EREADY rsrvd OBE2 IBF2 TIMEOUT rsrvd INT[1:0] PIBF POBE OBE IBF DRAFT COPY Lucent Technologies Inc. 5-19...
Page 175: Table 5-11. Alf Register
MINUS-ONE from BMU. evenp EVEN PARITY from BMU. oddp ODD PARITY from BMU. somef SOME FALSE from BIO. somet SOME TRUE from BIO. allf ALL FALSE from BIO. allt ALL TRUE from BIO. DRAFT COPY 5-20 Lucent Technologies Inc.
Page 176: External Memory Interface
Chapter 6 External Memory Interface...
Page 177: Figure 6-1.External Memory Interface
CHAPTER 6. EXTERNAL MEMORY INTERFACE CONTENTS 6 External Memory Interface ...........................6-1 EMI Function............................6-1 Programmable Features ........................6-13 Functional Timing ..........................6-14 6.3.1 Timing Action with Wait-States ..................6-15 Timing Examples ..........................6-17 6.4.1 CKO Timing ........................6-17 6.4.2 Write, Read, Read, W = 0 ....................6-18 6.4.3 Read, Write, Write, W = 0 ....................6-19 6.4.4...
Page 178: External Memory Interface
IO, or ERAMHI strobes. Therefore, with WEROM set, EROM appears in both Y space (replacing ERAM) and X space (in its X address range). If WEROM is active, DSEL will not be asserted. 1.DSEL not available in the DSP1627/28/29. DRAFT COPY Lucent Technologies Inc.
Page 179: Emi Function
5. CKO = CKI for crystal and small-signal options only. For the DSP1627/28/29, CKO = CKI even if PLL is selected as the internal clock source. 6. Sequenced wait-stated clock that completes two cycles during a sequenced external memory access. 1.DSEL not available in the DSP1627/28/29. DRAFT COPY Lucent Technologies Inc.
Page 180: Table 6-1. Dsp1611 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 181: Table 6-2. Dsp1617 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 182: Table 6-4. Dsp1618X24 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 183: Table 6-5. Dsp1627 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 184: Table 6-6. Dsp1627X32 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 185: Table 6-7. Dsp1628X08 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 186: Table 6-8. Dsp1628X16 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 187: Table 6-9. Dsp1629X10 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 188: Table 6-10. Dsp1629X16 Instruction/Coefficient Memory Map (X-Memory Space)
† MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. ‡ LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map.
Page 189: Table 6-11. Data Memory Map (Y-Memory Space)
Table 6-11. Data Memory Map (Y-Memory Space) Decimal Hexadecimal Address DSP1628 DSP1628 DSP1629 DSP1629 DSP1611 DSP1617/1618 DSP1627 Address in r0, r1, r2, r3 0x0000 RAM1 RAM1 RAM1 RAM1...
Page 190: Programmable Features
Logic sense of DSEL: Bit 6 in the ioc register selects the logic sense of the DSEL output. If one, it is active-high; if zero, it is active-low. 1.DSEL not available in the DSP1627/28/29. DRAFT COPY Lucent Technologies Inc. 6-13...
Page 191: Functional Timing
ERAMLO enable and the RWN pin. The flexibility of the wait-states in the DSP allows a wide range of memory speeds to be used. DB[15:0] AB[15:0] EROM PROGRAM DATA DSP1611/17/18/27/28/29 MEMORY MEMORY ERAMLO 5-4161 Figure 6-2. EMI Example DRAFT COPY 6-14 Lucent Technologies Inc.
Page 192: Timing Action With Wait-States
The selected enable goes high, but it can stay low if enabled on the next external memory cycle. The address bus changes if another external memory cycle starts next. Otherwise, the last valid external address is held. DRAFT COPY Lucent Technologies Inc. 6-15...
Page 193: Timing Action With Wait-States
The address bus changes if another external memory cycle starts next. Otherwise, the last valid external address is held. The data bus is held valid for one more CKO period unless an external read immediately follows in which case the bus will be 3-stated. DRAFT COPY 6-16 Lucent Technologies Inc.
Page 194: Timing Examples
X space and Y space in the same bank of RAM. The duty cycle will also be 50%. The CKO continues to follow the options in Table 6-14 during the sleep state induced by setting the AWAIT bit in the alf register. (FREE-RUNNING) (WAIT-STATED) EXTERNAL MEMORY CYCLE W = 1 5-4162 Figure 6-3. CKO Timing DRAFT COPY Lucent Technologies Inc. 6-17...
Page 195 Figure 6-4. Write, Read, Read, W = 0 Sample Instructions for the Above Sequence: *r0++=a0 Two-cycle write, r0 points to ERAMHI y=*r1++ One-cycle read, r1 points to ERAMHI x=*r1++ One-cycle read, r1 points to ERAMHI DRAFT COPY 6-18 Lucent Technologies Inc.
Page 196 Figure 6-5. Read, Write, Write, W = 0 Sample Instructions for the Above Sequence: y=*r0++ One-cycle read, r0 points to ERAMHI *r1++=a0 Two-cycle write, r1 points to ERAMHI *r1++=a0l Two-cycle write, r1 points to ERAMHI DRAFT COPY Lucent Technologies Inc. 6-19...
Page 197: Read, Write, W = 0, Compound Address
WRITE CYCLE W = 0 W = 0 ERAMLO READ WRITE ADDRESS ADDR. READ WRITE DATA DATA 5-4165 Figure 6-6. Read, Write, W = 0 Sample Instruction: *r0pz:y Compound read/write, r0 points to ERAMLO DRAFT COPY 6-20 Lucent Technologies Inc.
Page 198: Read W = 1, Read W = 2
Figure 6-7. Read, Read Sample Instructions: mwait=0x1002 /*EROM W=1, ERAMLO W=2 y=a1 x=*pt++ /*One-cycle read with W=1, pt points to EROM*/ a0=y /*One-cycle instruction, no action on EMI y=*r0++ /*One-cycle read with W=2, r0 points to ERAMLO*/ DRAFT COPY Lucent Technologies Inc. 6-21...
Page 199: Write W = 1
CKO period to maintain hold time for the external memory. WRITE CYCLE W = 1 ERAMLO ERAMLO ADDRESS ERAMLO DATA 5-4167 Figure 6-8. Write W = 1 Sample Instructions: mwait=0x0001 ERAMLO W=1 *r3++=a0 Two-cycle write with W=1, r3 points to ERAMLO DRAFT COPY 6-22 Lucent Technologies Inc.
Page 200: Read, Read With Delayed Enable
Figure 6-9. Read, Read, with Delayed Enable Sample Instructions: mwait=0x1002 EROM W=1, ERAMLO W=2 y=a1 x=*pt++ One-cycle read with W=1, pt points to EROM*/ p=x*y y=*r0++ Two-cycle read with W=2, r0 points to ERAMLO*/ DRAFT COPY Lucent Technologies Inc. 6-23...
Page 201: Write, Read, With Delayed Enable
WRITE DATA READ DATA 5-4169 Figure 6-10. Write, Read, with Delayed Enable, No Hold Time Sample Instructions: mwait=0x0001 ERAMLO W=2 *r0++=a0 Two-cycle write, r0 points to ERAMLO y=*r1++ One-cycle read, r1 points to ERAMLO DRAFT COPY 6-24 Lucent Technologies Inc.
Page 202: Boot-Up From External Rom
RSTB GOES HIGH SELECT INTERNAL SELECT HIGH MAP 2 MAP 1 INT1 WAIT- LOW ? STATES = 15 FETCH INSTR. TWICE FROM EROM, ADDR0 WAIT- STATES = 0 5-4170 Figure 6-11. External ROM Boot-Up DRAFT COPY Lucent Technologies Inc. 6-25...
Page 203: Memory Sequencer
ERAM access. Actually, after the instructions are loaded into cache, dual access disappears and the instruction fetch along with the additional cycles associated with the memory sequencer are avoided during the second through N iterations. Note: The reader is reminded that cache loops are noninterruptible. DRAFT COPY 6-26 Lucent Technologies Inc.
Page 204 A problem can occur if the code that purposely used an EMUXBOTH condition to cause an EMUXBOTH interrupt is ported from DSP1610/16 to DSP1611/17/18/27/28/29. Also, EMUXBOTH is missing from the DSP1611/17/18/27/28/29 interrupt vector table at 0x1C. DRAFT COPY Lucent Technologies Inc. 6-27...
Page 205: Downloading Code Into External Program Memory
Programming Example The following example assumes the PIO port of the DSP1617 is used to download code to the processor. The is in passive mode and is being driven by a host. Assume the processor is currently executing instructions in...
Page 206 /* If zero, code has been downloaded, goto done */ if eq goto done /* If not, clear page counter */ r1=0x0 /* Reset memory pointer */ r0=ERAMHI /* Clear EXTROM bit, leave WEROM intact */ ioc=0x800 /* Return */ ireturn DRAFT COPY Lucent Technologies Inc. 6-29...
Page 207 The counter c1 is used as a byte marker because only the DSP1617 has an 8-bit PIO. The r1 register is used as a marker to test whether 32K of code has been downloaded. The lower 32K of code is considered page 1, and the upper 32K is considered page 2.
Page 208: Serial I/O
Chapter 7 Serial I/O...
Page 209 CHAPTER 7. SERIAL I/O CONTENTS 7 Serial I/O ..............................7-1 SIO Operation ............................7-2 7.1.1 Active Clock Generator .......................7-2 7.1.2 Input Section ........................7-4 7.1.3 Output Section ........................7-6 User-Controlled Features........................7-9 The sioc Register .......................7-9 7.2.1 7.2.2 Loopback Control ......................7-11 7.2.3 Power Management ......................7-11 Serial I/O Pin Descriptions.......................7-12 Codec Interface..........................7-13 Serial I/O Programming Example ....................7-14...
Page 210: Figure 7-1.Serial I/O Internal Data Path
April 1998 7 Serial I/O The two serial I/O ports (SIO1 and SIO2) on the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 devices provide serial interfaces to multiple codecs and signal processors with little, if any, external hardware. The high-speed, double-buffered ports support back-to-back transmissions with data rates up to 25 Mbits/s for a 20 ns DSP if not in multiprocessor mode (check current data sheets for exact timing information).
Page 211: Sio Operation
2, 6, 8, 10 sioc(7, 8) sioc(3) sioc(2) sioc(9) DIV. BY sioc(5) sioc(4) DIV. OUTPUT INPUT BY 8, 16 SECTION SECTION tdms(9) tdms(0) SYNC 5-4172 † CKO is a free-running non-wait-stated clock. Figure 7-2. SIO Clocks DRAFT COPY Lucent Technologies Inc.
Page 212: Figure 7-3.Sio Active Mode Clock Timing
8 ICK/OCK CYCLES ICK/OCK shown with CKO/2 mode selected. ICK/OCK ILD/OLD SYNC 128/256 ICK/OCK CYCLES † For the DSP1627/28/29, this is the internal processor clock not CKI. 5-4173 Figure 7-3. SIO Active Mode Clock Timing DRAFT COPY Lucent Technologies Inc.
Page 213: Input Section
Figure 7-4 also shows how back-to-back reads are pipelined. LATCH B2 B3 B15 B0 B1 a0 = sdx 5-4174 Figure 7-4. SIO Passive Mode Input Timing, 16-bit Words DRAFT COPY Lucent Technologies Inc.
Page 214: Figure 7-5.Sio Active Mode Input Timing, 16-Bit Words
These bits are cleared when sdx is read. IBF is cleared on reset. For the DSP1617 only, the status of IBF can be read from either bit 4 or bit 15 of the pioc register or from bit 0 of the ins register (IBF interrupt status bit).
Page 215: Output Section
The OBE flag and signal are negated if the output buffer is reloaded via a write to the sdx register synchronized with a falling edge of CKO. B15 B0 B2 B3 SADD AD7 AS0 AS7 AD0 DOEN sdx = a0 sdx = a0 5-4176 Figure 7-6. SIO Passive Mode Output Timing, 16-bit Words 1.DSP1617 only. DRAFT COPY Lucent Technologies Inc.
Page 216: Figure 7-7.Sio Active Mode Output Timing, 16-Bit Words
OLD being supplied by the DSP). The primary difference from passive mode is that OCK now drives OLD and OLD is known to be a square wave. DRIVE 3-STATE B2 B3 SADD AD7 AS0 AS7 AD0 DOEN 5-4177 Figure 7-7. SIO Active Mode Output Timing, 16-bit Words DRAFT COPY Lucent Technologies Inc.
Page 217: Figure 7-8.Sio Passive Mode Output Timing, 8-Bit Words
OLD generators can only be set to ICK or OCK ÷ 16, active mode input and output in an 8-bit mode will proba- bly not be used. 3-STATE DRIVE B7 B0 B2 B3 SADD DOEN 5-4178 Figure 7-8. SIO Passive Mode Output Timing, 8-bit Words DRAFT COPY Lucent Technologies Inc.
Page 218: User-Controlled Features
7.2.1 The sioc Register Tables 7-1 through 7-3 show and define the control bits of the sioc register. During device reset, the sioc register bits are cleared. Table 7-1. Serial I/O Control (sioc) Register (DSP1611, DSP1617, and DSP1618 Only) 8—7 Field OLEN ILEN Table 7-2.
Page 219 0xDD00 (D = data). If the data is sent in the 8-bit mode with the MSB first (MSB = 1), the eight data bits are placed in the least significant half of sdx[in]; i.e., 0x00DD (D = data). DRAFT COPY 7-10 Lucent Technologies Inc.
Page 220: Loopback Control
SIO1 is not used or if reset can be used to re-enable the SIO1 unit. Otherwise, the first transaction after re-enabling the unit might be corrupted. Bit 6 of the powerc register (SIO2DIS) will power down the SIO2 unit. DRAFT COPY Lucent Technologies Inc. 7-11...
Page 221: Serial I/O Pin Descriptions
SYNC = ILD/OLD ÷ 8 or 16 corresponding to the setting of the SYNCSP field of the tdms register. This procedure can be used to generate a slow clock for SIO operation. † 3-stated. DRAFT COPY 7-12 Lucent Technologies Inc.
Page 222: Codec Interface
DSP device to an Lucent Technologies T7525 high-precision codec. In the first example, OCK of the DSP is active and ICK, ILD, and OLD are passive. The codec is in the nonmultiprocessor mode, although it can be used in the multiprocessor mode.
Page 223: Serial I/O Programming Example
When the first buffer fills, the two buffers are switched and the process repeats. 7.5.1 Program Segment Programming Examples Ping pong I/O routine for DSP1617 goto start .=0x2c intrpt...
Page 224: Multiprocessor Mode Description
(or time slots) for its turn to transmit. There are eight serial time slots with 16 bits of serial data in each time slot. DSP 0 DSP 1 DSP 7 DATA CK ADD SYN DATA CK ADD SYN DATA CK ADD SYN 5-4181 Figure 7-11. Multiprocessor Connections DRAFT COPY Lucent Technologies Inc. 7-15...
Page 225: Figure 7-12.Destination Address Communication
The transmitting DSP can send its unique source address and possibly other information describing the data. Figure 7-13 shows this case. TRANSMITTING DSP RECEIVING DSP saddx saddx PROTOCOL INFO. 5-4183 Figure 7-13. Protocol Channel Communication DRAFT COPY 7-16 Lucent Technologies Inc.
Page 226: Detailed Multiprocessor Mode Description
ILD and OLD signals in active mode. Although these signals are not required externally for the operation of multiprocessor mode, they are used internally in the SIO and must be active for that reason. DRAFT COPY Lucent Technologies Inc. 7-17...
Page 227: Figure 7-15.Multiprocessor Mode Time Slots
7-6). This is used to transmit information regarding the destination(s) of the data. The fully decoded receive address specified by the srta regis- ter receive address field (bits 15—8) determines which data is received. DRAFT COPY 7-18 Lucent Technologies Inc.
Page 228: Figure 7-16.Multiprocessor Mode Output Timing
This 8-bit protocol information will be latched into the high byte of saddx by all receiving DSPs with matching address, and this information is made available to the software by reading the saddx register: 15—8 7—0 Read from saddx AS[7—0] (Received AS) DRAFT COPY Lucent Technologies Inc. 7-19...
Page 229: Table 7-5. Time-Division Multiplex Slot (Tdms) Register
Transmit slot 1. SYNC Transmit slot 0. SYNC is an output (active mode). SYNC is an input (passive mode). † See sioc register, LD field in Table 7-1. ‡ Select this mode if in multiprocessor mode. DRAFT COPY 7-20 Lucent Technologies Inc.
Page 230: Table 7-6. Serial Receive/Transmit Address (Srta) Register
In this way, the destination DSP(s) need only act on information sent by the source DSP if it actually has new data available. Once the data becomes available, the transmission will wait until the next available time slot. DRAFT COPY Lucent Technologies Inc. 7-21...
Page 231 During time slot 5, the data in device 0 is transmitted on the TDM channel. Every device address is represented on the ADD line and all devices will accept the data. No actions in time slot 6. No actions in time slot 7. DRAFT COPY 7-22 Lucent Technologies Inc.
Page 232: Figure 7-17.Dsp1611/17/18/27/28/29 Multiprocessor Communications
= 0x2000 *r1++ = sdx a0 = sdx srta = 0x4000 a0 = sdx tdms = 0x101 srta = 0x8008 srta = 0x8008 a0 = sdx sdx = *r0++ 5-4128 Figure 7-17. DSP1611/17/18/27/28/29 Multiprocessor Communications DRAFT COPY Lucent Technologies Inc. 7-23...
Page 233: Suggested Multiprocessor Configuration
DSP16XXs on the bus. To prevent spurious inputs, the line should either be pulled up to V with a resistor, or the software should guarantee that some DSP is always driving in every time slot. If SYN is externally generated, a pull-up resistor will be required. 1.DSP1617 only. DRAFT COPY 7-24 Lucent Technologies Inc.
Page 234: Multiprocessor Mode Initialization
Once successful synchronization is achieved, the SYNC pulse is no longer necessary to keep the DSPs in step. The eight time slots are maintained even if the SYNC pulse ceases or occurs every 16 time slots. DRAFT COPY Lucent Technologies Inc. 7-25...
Page 235: Serial Interface #2
IN ioc REGISTER MULTIPLEXER IBF2 ILD2 ICK2 OCK2 OLD2 SYNC2 SADD2 OBE2 DOEN2 PIBF PIDS PCSN PSTAT PODS PBSEL POBE † † PSEL0 PSEL2 † PSEL1 † DSP1617 signal name. 5-4186.a Figure 7-18. SIO2—PIO/PHIF Multiplexing DRAFT COPY 7-26 Lucent Technologies Inc.
Page 236: Programmable Features
I/O data formats. The data can be 8 or 16 bits long and can be input/output MSB first or LSB first. Both input and output data formats can be independently configured. Table 7-8. sioc2 Register (DSP1611, DSP1617, and DSP1618 Only) 8—7...
Page 237: Parallel I/O (Dsp1617 Only)
Chapter 8 Parallel I/O (DSP1617 Only)
Page 238 CHAPTER 8. PARALLEL I/O CONTENTS 8 Parallel I/O (DSP1617 Only) ........................8-1 PIO Operation ............................8-2 8.1.1 Active Mode ........................8-2 8.1.2 PIO Interaccess Timing .......................8-5 8.1.3 Passive Mode ........................8-6 8.1.4 Peripheral Mode (Host Interface) ..................8-9 Programmer Interface ........................8-14 pioc Register Settings ......................8-16 8.2.1...
Page 239: Figure 8-1.Parallel I/O Unit
8 Parallel I/O (DSP1617 Only) The DSP1617 Parallel I/O (PIO) is an 8-bit interface for rapid transfer of data with external devices. Data rates up to 200 Mbits/s or 25 Mwords/s are supported by an instruction cycle of 20 ns. Minimal or no additional logic is required to interface with memory or other peripheral devices.
Page 240: Pio Operation
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.1 PIO Operation The PIO bus is an asynchronous interface. The PIO port characteristics are programmable and are controlled by the pioc. The PIO can be accessed in two basic modes: active or passive. In active mode, the DSP drives the data strobes (PIDS and PODS);...
Page 241: Figure 8-2.Active Mode Input Timing (Minimum Width Pids)
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.1 PIO Operation (continued) 8.1.1 Active Mode (continued) Active Mode Input The DSP drives PIDS, and the external device drives the PB. The active mode input transaction (see...
Page 242: Figure 8-3.Active Mode Output Timing (Minimum Width Pods)
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.1 PIO Operation (continued) 8.1.1 Active Mode (continued) Active Mode Output The DSP drives PODS and the PB. The active mode output transaction (see Figure 8-3) is initiated by the DSP if it executes a data move to one of the pdx channels (e.g., pdx0 = *r2).
Page 243: Pio Interaccess Timing
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.1 PIO Operation (continued) 8.1.2 PIO Interaccess Timing The DSP drives PODS and PIDS, and the DSP and external device alternate in driving the PB. Figure 8-4 shows the timing of mixed active mode inputs and outputs. (See Section 8.1.1, Active...
Page 244: Passive Mode
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.1 PIO Operation (continued) 8.1.3 Passive Mode In passive mode, the DSP can be used as a peripheral for other devices such as a microprocessor. Bits 12 and 11 of the pioc register configure the passive mode.
Page 245: Figure 8-5.Passive Mode Input Timing
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.1 PIO Operation (continued) 8.1.3 Passive Mode (continued) Passive Mode Input The external device drives PIDS and PB. For any passive mode access to the PIO, an external device must first pull the PSEL2 pin low. Then, the passive...
Page 246: Figure 8-6.Passive Mode Output Timing
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.1 PIO Operation (continued) 8.1.3 Passive Mode (continued) Passive Mode Output The external device drives PODS, and the DSP drives the PB. As mentioned above for any passive mode access to the PIO, an external device must first pull the PSEL2 pin low.
Page 247: Figure 8-7.The Dsp As A Microprocessor Peripheral
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.1 PIO Operation (continued) 8.1.4 Peripheral Mode (Host Interface) If both PIDS and PODS are in passive mode, the PIO is operating in peripheral mode. The PIO unit is designed to allow the user to interface the DSP as a peripheral to another processor.
Page 248: Table 8-3. The Pio Status Register, Pstat
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.1 PIO Operation (continued) 8.1.4 Peripheral Mode (Host Interface) (continued) Polling the PSTAT register (performed by holding PSEL1 high during a passive read) provides PIO status externally without requiring any extra pins. This register cannot be read or written under program control and is read only over the PB.
Page 249: Figure 8-8.Peripheral Mode Input Timing
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.1 PIO Operation (continued) 8.1.4 Peripheral Mode (Host Interface) (continued) Peripheral Mode Input The external device drives PIDS, PSEL2, and the PB. As with all passive accesses, an external device must start off by driving PSEL2 low enabling the PIO. If the flags are being monitored, this can be in response to PIBF or PSEL0 going low.
Page 250: Figure 8-9.Peripheral Output Mode Timing
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.1 PIO Operation (continued) 8.1.4 Peripheral Mode (Host Interface) (continued) Peripheral Mode Output The external device drives PODS, PSEL1, and PSEL2; and the DSP drives the PB. As with all passive accesses, an external device must start off by driving PSEL2 low enabling the PIO. If the flags are being monitored, this can be in response to PIBF or PSEL0 going low.
Page 251: Figure 8-10.Polling Pstat Timing
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.1 PIO Operation (continued) 8.1.4 Peripheral Mode (Host Interface) (continued) Polling the PSTAT Register Polling the PSTAT register (see Figure 8-10) is identical to a passive or peripheral mode output. The main differ- ence is the PSEL1 pin must be held high while PODS is asserted.
Page 252: Programmer Interface
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.2 Programmer Interface The PIO port can be accessed with the data move group of instructions. The eight logical ports (pdx0—pdx7) cor- respond to the encoding on the 3-bit field formed by the pins PSEL[2:0]. For example, an access to pdx3 will result in the 3-bit field 011 appearing on the three pins (PSEL[2:0]) in active-active mode.
Page 253: Table 8-6. Pio Control (Pioc) Register
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.2 Programmer Interface (continued) The PIO control (pioc) register (see Table 8-6) is a 16-bit, user-accessible register used to configure some features of the PIO: External device access time.
Page 254: Pioc Register Settings
Many of the bit fields in the pioc deal with interrupts. Before going any further the reader should be aware that in addition to the interrupt control provided by the pioc, interrupts in the DSP1617 can be controlled through the inc register in the CONTROL block.
Page 255: Latent Reads
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.2 Programmer Interface (continued) 8.2.2 Latent Reads While in active mode, reading from a logical PIO port is accomplished by an actual read of the single physical port on the DSP.
Page 256: Figure 8-11.Pio Latent Reads Hardware
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.2 Programmer Interface (continued) 8.2.2 Latent Reads (continued) PIDS STROBES EXTERNAL DEVICE PB (8) pdx [IN] DSP1617 5-4196 Figure 8-11. PIO Latent Reads Hardware VALID PSEL[2:0] PIDS VALID...
Page 257: Power Management
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.2 Programmer Interface (continued) 8.2.3 Power Management Bit 5 of the powerc register (PIO1DIS) is a powerdown signal to the PIO I/O unit. It disables the clock input to the unit, thus eliminating any sleep power associated with the PIO.
Page 258 DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.3 Interrupts and the PIO (continued) Bits 4—0 of the pioc indicate whether an interrupt was generated by IBF, OBE, PIDS, PODS, or INT0. These bits can be read by an interrupt service routine to determine which interrupt(s) have occurred and, hence, how to pro- ceed to service the interrupt request.
Page 259: Pio Signals
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 Parallel I/O (DSP1617 Only) 8.4 PIO Signals Table 8-7. PIO Signals † Symbol Type Name/Description ‡ PIO Data Bus. This 8-bit bidirectional bus is used to input data to or output data PB[7:0] from the PIO.
Page 260: Pio Pin Multiplexing
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Parallel I/O (DSP1617 Only) April 1998 8.4 PIO Signals (continued) 8.4.1 PIO Pin Multiplexing The PIO pins are multiplexed with BIO and SIO pins. The PIO functions are selected at the pins by clearing bit 10, (ESIO2) in the ioc register.
Page 261: Parallel Host Interface (Phif) (Dsp1611/18/27/28/29 Only)
Chapter 9 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
Page 262: Figure 9-1.Parallel Host Interface
CHAPTER 9. PARALLEL HOST INTERFACE (PHIF) (DSP1611/18/27/28/29 ONLY) CONTENTS 9 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) ...............9-1 PHIF Operation ..........................9-2 Intel Mode, 16-Bit Read ......................9-3 9.1.1 9.1.2 Intel Mode, 16-Bit Write ......................9-4 9.1.3 Motorola Mode, 16-Bit Read ....................9-5 9.1.4 Motorola Mode, 16-Bit Write ....................9-6 9.1.5 8-Bit Transfers ........................9-7 9.1.6...
Page 263: Parallel Host Interface (Phif) (Dsp1611/18/27/28/29 Only)
9 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) The PHIF is an 8-bit parallel port that can interface to an 8-bit bus containing other Lucent Technologies DSPs (e.g., DSP1611, DSP1616, DSP1628, . . . ), microprocessors, or peripheral I/O devices. The PHIF port supports either Motorola or Intel protocols as well as 8- or 16-bit transfers configured in software.
Page 264: Phif Operation
The interface selection is made by writing the ESIO2 bit in the ioc register (see Section 9.4, PHIF Pin Multiplexing). A zero value for ESIO2 selects the PHIF pins and is the default setting after device reset. DRAFT COPY Lucent Technologies Inc.
Page 265: Intel Mode, 16-Bit Read
† PBSEL PB, FROM DSP † POBE LOW BYTE READ HIGH BYTE READ † The logic levels of these pins can be inverted by programming the phifc register. 5-4495 Figure 9-2. Intel Mode, 16-Bit Read DRAFT COPY Lucent Technologies Inc.
Page 266: Intel Mode, 16-Bit Write
PBSEL PB, FROM EXTERNAL DEVICE † PIBF LOW BYTE WRITE HIGH BYTE WRITE † The logic levels of these pins can be inverted by programming the phifc register. 5-4496 Figure 9-3. Intel Mode, 16-Bit Write DRAFT COPY Lucent Technologies Inc.
Page 267: Motorola Mode, 16-Bit Read
EXTERNAL DEVICE PBSE PB, FROM DSP † POBE LOW BYTE READ HIGH BYTE READ † The logic levels of these pins can be inverted by programming the phifc register. 5-4497 Figure 9-4. Motorola Mode, 16-Bit Read DRAFT COPY Lucent Technologies Inc.
Page 268: Motorola Mode, 16-Bit Write
PBSEL PB, FROM EXTERNAL DEVICE PIBF † LOW BYTE WRITE HIGH BYTE WRITE † The logic levels of these pins can be inverted by programming the phifc register. 5-4498 Figure 9-5. Motorola Mode, 16-Bit Write DRAFT COPY Lucent Technologies Inc.
Page 269: 8-Bit Transfers
In Intel mode, this bit is set if PODS latches data into pdx0(OUT). In Motorola mode, this bit is set if PDS latches data into pdx0(OUT). In both cases, it is cleared when the DSP writes pdx0(OUT). DRAFT COPY Lucent Technologies Inc.
Page 270: Programmer Interface
If PSTROBE = 1, PODS pin (PDS) active-high. PSTROBE Intel protocol: PIDS and PODS data strobes. Motorola protocol: PRWN and PDS data strobes. PMODE 8-bit data transfers. 16-bit data transfers. † See Table 9-3 on page 9 for selecting high byte. DRAFT COPY Lucent Technologies Inc.
Page 271: Table 9-3. Phifc Register Phif Function (8-Bit And 16-Bit Modes)
PFLAGSEL, if set to a one, causes both the PIBF and the POBE flags to appear on the PIBF pin by ORing PIBF and POBE together. The POBE pin is unchanged. This allows the single pin (PIBF) to be used to indicate the tim- ing. DRAFT COPY Lucent Technologies Inc.
Page 272: Power Management
DSP program reads pdx0 either inside or outside an interrupt routine. POBE (ins[2]) indicates that an external device has read from the DSP's pdx0(OUT) register. POBE is cleared when the DSP program writes pdx0 either inside or outside an interrupt routine. DRAFT COPY 9-10 Lucent Technologies Inc.
Page 273: Phif Pin Multiplexing
(ioc Register bit 10) for (ioc Register bit 10) ESIO2 = 1 ESIO2 = 0 IOBIT3 IOBIT2 IOBIT1 IOBIT0 SADD2 DOEN2 ICK2 OBE2 POBE IBF2 PIBF OLD2 PODS ILD2 PIDS SYNC2 PBSEL PSTAT OCK2 PCSN DRAFT COPY Lucent Technologies Inc. 9-11...
Page 274: Overall Functional Timing
F: POBE is reset as the output buffer is written by the DSP. The external device can again strobe PODS. G: The read cycle can then repeat. At least seven instruction cycles are required for the total read cycle. POBE PODS 5-4499 Figure 9-6. Overall PHIF Read Cycle DRAFT COPY 9-12 Lucent Technologies Inc.
Page 275 Chapter 10 Bit I/O Unit...
Page 276 CHAPTER 10. BIT I/O UNIT CONTENTS 10 Bit I/O Unit..............................10-1 10.1 BIO Hardware Function ........................10-1 10.1.1 BIO Configured as Inputs ....................10-2 10.1.2 BIO Configured as Outputs ....................10-2 10.1.3 Pin Descriptions ........................10-3 10.1.4 BIO Pin Multiplexing ......................10-4 10.2 Software View ..........................10-4 10.2.1 Registers ...........................10-5 10.2.2...
Page 277: Bio Hardware Function
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 10 Bit I/O Unit The Bit I/O (BIO) Unit for the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 provides eight bidirectional pins for monitor or control functions. The pins are multiplexed with the PIO /PHIF and interrupt state pins.
Page 278: Bio Configured As Inputs
DATA field means leave the output unchanged. If a bit in the MODE field is a zero, it selects the data mode for which a one in the DATA field becomes an output one and a zero becomes an output zero. DRAFT COPY 10-2 Lucent Technologies Inc.
Page 279: Pin Descriptions
Each of these bits can be independently configured as either an output or an input. As outputs, they can be inde- pendently set, toggled, or cleared under program control. As inputs, they can be tested independently or in combi- nations for various data patterns. Symbol Type Name/Function IOBIT[7:0] Status/Control Bits 0—7 DRAFT COPY Lucent Technologies Inc. 10-3...
Page 280: Bio Pin Multiplexing
DATA = ? DATA = ? PATTERN IGNORE MATCH ? INPUT NO CHANGE 1 TO FLAG SETTING TOGGLE 0 TO ON OUTPUT OUTPUT LOGIC OUTPUT OUTPUT 5-4204 Figure 10-4. Logic Flow Diagram for BIO Configuration DRAFT COPY 10-4 Lucent Technologies Inc.
Page 281: Registers
For a pin in the output mode, an internal register stores a value for the output from the most recent write of cbit. These internal registers are initialized to zero after reset. DRAFT COPY Lucent Technologies Inc. 10-5...
Page 282: Flags
/* test the entire BIO byte for 0xab if allt goto pass /* if (BIO==0xab) branch to label pass cbit=0x0302 /* test the bottom 2 bits for 0x2 if somet a0h=a0h+1/* if either bit matches, increment a0 DRAFT COPY 10-6 Lucent Technologies Inc.
Page 283 /* if (BIO[3—0]==0xb) branch Note: In the last example, outputs can be set and inputs can be tested at the same time with one single write to the cbit register. DRAFT COPY Lucent Technologies Inc. 10-7...
Page 284 Chapter 11 JTAG Test Access Port...
Page 285 CHAPTER 11. JTAG TEST ACCESS PORT CONTENTS 11 The JTAG Test Access Port........................11-1 11.1 Overview of the JTAG Architecture ....................11-1 11.2 Overview of the JTAG Instructions....................11-3 11.3 Elements of the JTAG Test Logic .....................11-4 11.3.1 The Test Access Port (TAP) ....................11-4 11.3.2 The TAP Controller ......................11-5 11.3.3...
Page 286: The Jtag Test Access Port
11 The JTAG Test Access Port The DSP1611, DSP1617, DSP1618, and DSP1627 have a standard four-pin test access port known as JTAG. The DSP1628, and DSP1629 have a five-pin test access port; the standard four-pin JTAG test access port plus an additional TRST pin.
Page 287: Figure 11-2.The Tap Controller State Diagram
1 of 16 different instruction codes. The JTAG instructions and their detailed functions are pre- sented in Section 11.4, The JTAG Instruction Set. The physical structure of the JIR is covered in Section 11.3.3, The Instruction Register—JIR. DRAFT COPY 11-2 Lucent Technologies Inc.
Page 288: Overview Of The Jtag Instructions
Private Reserved for HDS use. JTGW3 Private Reserved for HDS use. JTGR3 Private Reserved for HDS use. JUSR1 Private Reserved for HDS use. IDCODE Public Select Device ID register. BYPASS Public Select BYPASS register. DRAFT COPY Lucent Technologies Inc. 11-3...
Page 289: Elements Of The Jtag Test Logic
If asserted low, TRST asynchronously resets the JTAG TAP controller. In an application environment, this pin must be asserted prior to or concurrent with RSTB. This pin is internally pulled up to avoid unwanted resetting of the TAP controller. 1.DSP1628/29 only. DRAFT COPY 11-4 Lucent Technologies Inc.
Page 290: The Tap Controller
Update xR: In this state, data from the shift register stage of the register is loaded into the latched parallel outputs (if any) that remain stable during shift operations. This is the terminal state in a scan operation. DRAFT COPY Lucent Technologies Inc. 11-5...
Page 291: Figure 11-3.Timing Diagram Example
DSP from TDI. (TDI changes on the falling edge of TCK and the DSP strobes TDI on the rising edge.) After four shifts, the new data is lined up in the DSP and is parallel loaded to the TDR output on the falling edge of TCK in the middle of the UPDATE DR state. DRAFT COPY 11-6 Lucent Technologies Inc.
Page 292: The Instruction Register-Jir
(LSB) to be the one closest to the TDO pin. According to this definition, the data should be shifted in LSB first if shifting data into a register through TDI. Figure 11-4. The JTAG Instruction Register/Decoder Structure DRAFT COPY Lucent Technologies Inc. 11-7...
Page 293: The Boundary-Scan Register-Jbsr
Table 11-2. Boundary-Scan Register Cell Type Definitions Cell Type Meaning Input Cell. 3-state Output Cell. Bidirectional (I/O) Cell. 3-state Controller Cell. Bidirectional Controller Cell. Tables 11-3 11-4 show the configuration of the boundary-scan register. DRAFT COPY 11-8 Lucent Technologies Inc.
Page 294: Table 11-3. Jtag Scan Register (Dsp1611, 1617 And 1618 Only)
Multiplexing, Section 9.4, PHIF Pin Multiplexing, Section 8.2.3, Power Management, and Section 7.7.1, SIO2 Features. § Indicates signal is internal and not necessarily observable at pins depending on how the JTAG is set up. DRAFT COPY Lucent Technologies Inc. 11-9...
Page 295: Table 11-4. Jtag Scan Register (Dsp1627/28/29 Only)
§ Indicates signal is internal and not necessarily observable at pins depending on how the JTAG is set up. If the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin. DRAFT COPY 11-10 Lucent Technologies Inc.
Page 296: Figure 11-5.The Simplest Boundary-Scan Register Cell
11-5. The JBSR is then formed by stacking such four-terminal units on top of each other. SERIAL OUTPUT CAPTURE-DR SHIFT-DR PARALLEL OUTPUT PARALLEL INPUT UPDATE-DR MODE SERIAL INPUT 5-4206 Figure 11-5. The Simplest Boundary-Scan Register Cell DRAFT COPY Lucent Technologies Inc. 11-11...
Page 297 A single OE cell can drive multiple outputs as, for example, in buses. For example, Table 11-3 shows that the register cell number 99 controls the 3- state buffer of many output cells. DRAFT COPY 11-12 Lucent Technologies Inc.
Page 298: Figure 11-6.Cell Interconnections For A 3-State Pin
11.3.4 The Boundary-Scan Register—JBSR (continued) TO NEXT CELL O CELL OUTPUT BUFFER CHIP OUTPUT OUTPUT OUTPUT PIN OE CELL CHIP OUTPUT ENABLE PIN OUTPUT ENABLE FROM PREVIOUS CELL 5-4207 Figure 11-6. Cell Interconnections for a 3-State Pin DRAFT COPY Lucent Technologies Inc. 11-13...
Page 299: Figure 11-7.Bidirectional Cell
HOLI. Instead, it is driven by OE that is the same as HOLI except dur- ing INTEST when it is a zero. This will put the biputs in the high-impedance state during internal tests and, thus, prevent them from causing contention on external buses. DRAFT COPY 11-14 Lucent Technologies Inc.
Page 300: Figure 11-8.Cell Interconnections For A Bidirectional Pin
B CELL OUTPUT OUTPUT FROM CHIP BIDIRECTIONAL HOLI INPUT INPUT TO CHIP DC CELL HOLI BIDIRECTIONAL PIN BIDIRECTIONAL ENABLE ENABLE FROM CHIP FROM PREVIOUS CELL 5-4208 Figure 11-8. Cell Interconnections for a Bidirectional Pin DRAFT COPY Lucent Technologies Inc. 11-15...
Page 301: The Bypass Register-Jbpr
The JTAG device identification register can be used to unambiguously determine the manufacturer of a component and to provide other descriptive information. As shown in Figure 11-9, the 32 bits of the JIDR are arranged into three fields. DRAFT COPY 11-16 Lucent Technologies Inc.
Page 302: Table 11-5. Jidr Field Descriptions Dsp1617/18/27/28/29
JEDEC standard manufacturer's identification code. The assigned Lucent Technologies identification code is 0x03B. Part Number Field: Bits 18—12 contain the DSP1617/18/27/28/29 unique part number. The ROM code is con- tained in bits 27—19. The Version Field: Bits 31—28 contain the RESERVED, SECURE, and CLOCK fields as described in Table 11-5.
Page 303: Table 11-6. Jidr Field Descriptions Dsp1611
A description of each field for the DSP1611 only follows: The Manufacturer Identity Field: Bits 11—0 of the JIDR make up the manufacturer identity field containing a compressed form of the JEDEC standard manufacturer's identification code. The assigned Lucent Technologies identification code is 0x03B.
Page 304: The Jtag Data Register-Jtag
JBSR register, and the inputs to the device are driven by the boundary-scan I-type cells. With MODE equals one and in the capture-DR state, the state of the outputs from the device logic is captured by the JBSR and can be shifted out for inspection. DRAFT COPY Lucent Technologies Inc. 11-19...
Page 305: The Sample Instruction
The instruction regis- ter is initialized to hold the IDCODE value (i.e., 0xE) when entering the test-logic-reset state (e.g., at powerup) as required by the standard. DRAFT COPY 11-20 Lucent Technologies Inc.
Page 306: Timer
Chapter 12 Timer...
Page 307 CHAPTER 12. TIMER CONTENTS 12 Timer ................................12-1 12.1 Hardware View..........................12-1 12.2 Programmable Features and Operation...................12-2 12.2.1 timerc Register Encoding ....................12-2 12.2.2 timer0 Register .........................12-3 12.2.3 The inc Register .......................12-3 12.2.4 Initialization Conditions .....................12-3 12.3 Program Example ..........................12-4 12.4 Timing ..............................12-5...
Page 308: Hardware View
IDB bus at any time transferring the current state of the counter. The period register stores the beginning count for the repeat mode and is loaded by a write to timer0. DRAFT COPY Lucent Technologies Inc. 12-1...
Page 309: Programmable Features And Operation
819.2 µs 1110 CKO/32768 1.092 ms 1111 CKO/65536 2.185 ms 1.6384 ms † CKO = free-running non-wait-stated clock. ‡ The DSP1627/28/29 period is based on the internal clock selected (PLL, CKI, or ring oscillator). DRAFT COPY 12-2 Lucent Technologies Inc.
Page 310: Timer0 Register
CKO/2, turns off the reload feature, disables timer counting, and initializes the timer value to its quiescent state. The act of resetting the device does not cause the timer to interrupt the DSP. The period regis- ter is not initialized on reset. DRAFT COPY Lucent Technologies Inc. 12-3...
Page 311: Program Example
/* temporarily turn off timer clock to hold count*/ /* perform nontimed function timerc=0x34 /* restore clocking to timer /* continue with main routine tmrint:. /* Timer interrupt routine here timer0=NNNN /* optionally change timer period to new value ireturn DRAFT COPY 12-4 Lucent Technologies Inc.
Page 312: Timing
If an interrupt is being serviced and the same interrupt is pending next, the interrupt must remain asserted into the next rising edge of IACK. (See Section 3.4.4, Interrupt Operation.) DRAFT COPY Lucent Technologies Inc. 12-5...
Page 313 Chapter 13 Bit Manipulation Unit...
Page 314 CHAPTER 13. BIT MANIPULATION UNIT CONTENTS 13 Bit Manipulation Unit (BMU) ........................13-1 13.1 Hardware View..........................13-1 13.2 Software View ..........................13-2 13.2.1 Instruction Set ........................13-2 13.2.2 Shifting Operations ......................13-2 13.2.3 Normalization ........................13-4 13.2.4 Extraction ..........................13-5 13.2.5 Insertion ..........................13-6 13.2.6 Shuffle Accumulators ......................13-8 13.2.7 Instruction Encoding ......................13-9 13.2.8...
Page 315: Bit Manipulation Unit (Bmu)
REGISTERS aa0, aa1 ALTERNATE ACCUMULATORS CONTROL a0, a1 BMU SHIFT, MAIN ACCUMULATORS EXTRACT, INSERT, IN DAU NORMALIZE, FIND EXPONENT FLAGS nmns1, mns1, oddp, evenp LMI, LEQ, LLV, LMV 5-4212 Figure 13-1. BMU Block Diagram DRAFT COPY Lucent Technologies Inc. 13-1...
Page 316: Software View
In the logical right shift (>>> ) bits 31—0 of the source accumulator are shifted to the right into the destination accumulator. The open upper bits after the shift are filled in with zeros. BEFORE LOGICAL RIGHT SHIFT 32 31 16 15 AFTER 0----------------0 5-4213 Figure 13-2. Logical Right Shift DRAFT COPY 13-2 Lucent Technologies Inc.
Page 317: Figure 13-3.Left Shifts
For right shifts, LLV is true if the shift amount is greater than 35 bits. Note:A logical right shift of 32 bits or greater will fill the destination accumulator with zeros. Stored in bit 13 of the psw register. DRAFT COPY Lucent Technologies Inc. 13-3...
Page 318: Normalization
(M = 0, 1, 2, or 3) registers. The number in aS is normalized and placed in aD with the sign bit in bit 31. aS is left unchanged. The flags (described Section 13.2.2, Shifting Operations) are set based on the value written into aD. DRAFT COPY 13-4 Lucent Technologies Inc.
Page 319: Extraction
The eight flags (described Section 13.2.2, Shifting Operations) are set based on the value written into aD with their normal definitions, except LLV is true if WIDTH = 0 or if (WIDTH + OFFSET) > 36. DRAFT COPY Lucent Technologies Inc. 13-5...
Page 320: Insertion
The original bits in aD not in the new field are unaffected. SOURCE ACCUMULATOR WIDTH SPECIFIED IN IMMEDIATE OR arM OFFSET SOURCE 2 & aS, aD DESTINATION ACCUMULATOR 5-4216 Figure 13-6. Insertion, Case 1. Source and Destination Accumulators Different DRAFT COPY 13-6 Lucent Technologies Inc.
Page 321: Figure 13-7.Insertion, Case 2. Source And Destination Accumulators Are The Same
The eight flags (described Section 13.2.2, Shifting Operations) are set based on the value written into aD with their normal definitions, except LLV is true if WIDTH = 0 or if (WIDTH + OFFSET) > 36. DRAFT COPY Lucent Technologies Inc. 13-7...
Page 322: Shuffle Accumulators
Figure 13-8 shows the shuffle instruction. Flags (described Section 13.2.2, Shifting Operations) are set based on the value written into aD. SOURCE ACCUMULATOR ALTERNATE ACCUMULATOR DESTINATION ACCUMULATOR 5-4217 Figure 13-8. Shuffle Accumulators DRAFT COPY 13-8 Lucent Technologies Inc.
Page 323: Instruction Encoding
01xx aD = extractz (aS, arM) 1110 1000 aD = insert (aS, IM16) 1010 10xx aD = insert (aS, arM) 0111 0000 aD = aS : aa0 0111 0001 aD = aS : aa1 DRAFT COPY Lucent Technologies Inc. 13-9...
Page 324: Software Example
Puts (2M+33) 2 into a1h by shifting left N times a1=a1-y Puts (2M+33) 2 –33 into a1h a0=a0>>23 Puts sign bit in bit 0, 1s in 1—35 if mns1 a1=-a1 If negative, take two's complement return DRAFT COPY 13-10 Lucent Technologies Inc.
Page 325 Chapter 14 Error Correction Coprocessor (DSP1618/28 Only)
Page 326 CHAPTER 14. ERROR CORRECTION COPROCESSOR (DSP1618/28 ONLY) CONTENTS 14 Error Correction Coprocessor (DSP1618/28 Only) ..................14-1 14.1 System Description..........................14-1 14.2 Hardware Architecture ........................14-3 14.2.1 Branch Metric Unit ......................14-3 14.2.2 Update Unit ........................14-4 14.2.3 Traceback Unit ........................14-4 14.2.4 Interrupts and Flags ......................14-5 14.2.5 Traceback RAM .........................14-5 14.3 DSP Decoding Operation Sequence ....................14-6...
Page 327: System Description
In wideband low data rate applications, additive white Gaussian noise (AWGN) is the principle channel impairment. Under these conditions, Euclidean branch metric computation for convolutional decoding is selected by resetting the branch metric select bit to zero. A traceback-length register is provided for programming the traceback decode length. DRAFT COPY Lucent Technologies Inc. 14-1...
Page 328: Figure 14-1.Error Correction Coprocessor Block Diagram/Programming Model
(DSR). All internal states of these memory-mapped registers are accessible and controllable by the DSP program. However, during periods of simultaneous DSP core and ECCP activity, ECCP internal registers and the shared bank RAM4 are not accessible to the user's DSP code. DRAFT COPY 14-2 Lucent Technologies Inc.
Page 329: Hardware Architecture
Generating polynomials G(0), . . . , G(5) (up to six-delays corresponding to a constraint length of seven) can take part in computing the estimated received signals E(0, k), . . . , E(5, k) associated with all possible state transitions k = 0, 1, 2 – 1. DRAFT COPY Lucent Technologies Inc. 14-3...
Page 330: Update Unit
ACC j p If the end state is known, the traceback decoding can be forced in the direction of the right path by writing the desired end state into the minimum cost index register (MIDX). DRAFT COPY 14-4 Lucent Technologies Inc.
Page 331: Interrupts And Flags
ECCP. RAM4, located in the Y-memory space in the address range 0x0C00 to 0x0FFF, is used by the ECCP for storing traceback information. If the ECCP is active (i.e., the EBUSY flag is asserted), the DSP core cannot access this traceback RAM. DRAFT COPY Lucent Technologies Inc. 14-5...
Page 332: Dsp Decoding Operation Sequence
ACCEPT TL VALID DECODED VALID DECODED SYMBOL N – TL + 1 TRACEBACK INSTR 1 SYMBOLS EXECUTE TL TRACEBACK INSTRUCTIONS TRACEBACK INSTR TL VALID DECODED SYMBOL N 5-4501 Figure 14-2. DSP Core Operation Sequence DRAFT COPY 14-6 Lucent Technologies Inc.
Page 333: Operation Of The Eccp
STORE SURVIVOR PATH INCREMENT VITERBI TRACEBACK K BY ONE INSTR. DECODING COMPLETE DECREMENT TBLR BY ONE OUTPUT (C – 1) DECODED SYMBOL K < 2 – 1 SYMBOLS DECODED 5-4502 Figure 14-3. ECCP Operation Sequence DRAFT COPY Lucent Technologies Inc. 14-7...
Page 334: Software Architecture
Each time the core accesses an internal ECCP register through edr, the content of the ear register is postincre- mented by one. During a DSP compound addressing instruction, the same edr register is accessed for both the read and the write operation. DRAFT COPY 14-8 Lucent Technologies Inc.
Page 335: Table 14-2. Eccp Instruction Encoding
DSP code will be blocked. The eir register can be read during ECCP activity. The ECCP address reg- ister, ear, can be read or written during ECCP activity to set up the ECCP address for the next edr access after the completion of the ECCP instruction. DRAFT COPY Lucent Technologies Inc. 14-9...
Page 336: Eccp Internal Memory-Mapped Registers
Bits 7:0 are HQ4. Bits 15:8 are HI4. 0x405 Received Symbol/ Convolutional decoding case: Channel Tap Register Bits 7:0 are reserved. S3H3 Bits 15:8 are S3. MLSE equalization case: Bits 7:0 are HQ3. Bits 15:8 are HI3. DRAFT COPY 14-10 Lucent Technologies Inc.
Page 337 Bits 15:10 are reserved. 0x40C Generating Polynomial Convolutional case: Bits 7:0 are G4. Bits 15:8 are G5. MLSE case: Bits 15:0 are reserved. 0x40D Minimum Cost Index Register Bits 7:0 are used. MIDX Bits 15:8 are reserved. DRAFT COPY Lucent Technologies Inc. 14-11...
Page 338: Table 14-5. Control Fields Of The Control Register
2 to 6. For soft decision convolutional decoding or MLSE equalization, constraint lengths from 2 to 6 are supported. This constraint length field is defined in the following table. Bits Constraint # of PS/NS ECON(14—12) Length Registers Reserved Reserved DRAFT COPY 14-12 Lucent Technologies Inc.
Page 339 Soft Decoded Output Definition: Two types of 8-bit soft-decoded output are implemented. One is the coded sur- vivor incremental branch metric, and the other is the coded accumulated path cost difference. DRAFT COPY Lucent Technologies Inc. 14-13...
Page 340 0), only values in the range of 1 to 31 are legal. While in the hard decision mode (ECON.SH = 1), only values in the range of 1 to 63 are legal. TBLR Bits 15—6 5—0 Function Reserved Traceback length (0-63) DRAFT COPY 14-14 Lucent Technologies Inc.
Page 341 Depending on the code rate set in the control register, the appropriate number of generating polynomi- als will be used in the branch metric calculation. ZIG10 Bits 9—8 1—0 Function Reserved Reserved DRAFT COPY Lucent Technologies Inc. 14-15...
Page 342 (n), i = 0, 1, . . . , 5) in 8-bit binary magnitude form. For MLSE equalization, the high byte stores in-phase channel estimate coefficients HI(n) in 8-bit two's complement form and the low byte stores the quadrature compo- nents HQ(n) in 8-bit two's complement form. Bits 15—8 7—0 MLSE Function Convolve Function Reserved DRAFT COPY 14-16 Lucent Technologies Inc.
Page 343: Eccp Interrupts And Flags
ECCP activity either by polling the EBUSY flag and waiting for its negation or by waiting for the EREADY interrupt to be asserted. In the later case, RAM4 can be accessed by the EREADY interrupt service routine. DRAFT COPY Lucent Technologies Inc. 14-17...
Page 344 /* Now can access ECCP and/or RAM4 .=0x0C00+offset /* Offset to avoid conflict with ECCP program_eccp: /* Load various ECCP registers here eir=UpdateMLSE /* Invoke ECCP instruction pt=OutofRAM4 /* Address outside RAM4 goto pt /* Jump out of RAM4 DRAFT COPY 14-18 Lucent Technologies Inc.
Page 345: Eccp Instruction Timing
Max 0 [ TBLR 2 UpdateMLSE SH – – where CL represents the value of the constraint length field in the ECON register and TBLR is the traceback length value programmed into the TBLR register. DRAFT COPY Lucent Technologies Inc. 14-19...
Page 346: Table 14-6. Representative Updatemlse Instruction Cycles (Sh = 0)
31. TBLR values greater than 31 are illegal and must not be used with the UpdateMLSE instruction if soft decision mode is selected. Table 14-6. Representative UpdateMLSE Instruction Cycles (SH = 0) TBLR Cycles 1—7 1—10 1—16 1—28 1—31 DRAFT COPY 14-20 Lucent Technologies Inc.
Page 347: Updatemlse Instruction With Hard Decision
Table 14-7. Representative UpdateMLSE Instruction Cycles (SH = 1) TBLR Cycles 1—7 1—11 1—19 1—35 1—63 For the UpdateMLSE instruction with hard decision, the traceback length register can be programmed to a maxi- mum value of 63. DRAFT COPY Lucent Technologies Inc. 14-21...
Page 348: Updateconv Instruction With Soft Decisions
Table 14-8. Representative UpdateConv Instruction Cycles (SH = 0) TBLR Cycles 1—6 1—9 1—15 1—27 1—31 Similar to the UpdateMLSE, the traceback length can attain a maximum value of 31 with the soft decision mode programmed (i.e., with ECON.SH = 0). DRAFT COPY 14-22 Lucent Technologies Inc.
Page 349: Updateconv Instruction With Hard Decision
UpdateConv instructions with soft decision symbols. A maximum value of 63 can be pro- grammed for hard decision decoding after UpdateMLSE or UpdateConv instructions. The contents of the TBLR register are autodecremented after the TraceBack instruction is completed. DRAFT COPY Lucent Technologies Inc. 14-23...
Page 350: Interface Guide
Chapter 15 Interface Guide...
Page 351 Powerup Reset .......................15-12 15.3.2 Using the TAP to Reset the TAP Controller ..............15-12 15.3.3 RSTB Pin Reset ......................15-13 15.4 Mask-Programmable Options ......................15-14 15.4.1 Input Clock Options ......................15-14 15.4.2 ROM Security Options (DSP1617/18/27/28/29 Only) .............15-14 15.5 Additional Electrical Characteristics and Requirements for Crystal..........15-15...
Page 352: Pin Information
‡‡For DSP1611/18: PSEL0 is PBSEL, PSEL1 is PSTAT, and PSEL2 is PCSN. §§3-stated if RSTB = 0 and INT0 = 1. Output = CKI (1x) or CKI/2 (2x) if RSTB = 0 and INT0 = 0. DRAFT COPY Lucent Technologies Inc. 15-1...
Page 353 ‡‡For DSP1611/18: PSEL0 is PBSEL, PSEL1 is PSTAT, and PSEL2 is PCSN. §§3-stated if RSTB = 0 and INT0 = 1. Output = CKI (1x) or CKI/2 (2x) if RSTB = 0 and INT0 = 0. DRAFT COPY 15-2 Lucent Technologies Inc.
Page 354: Table 15-2. Dsp1627/28/29 Pin Descriptions
††For SIO multiprocessor applications, add external pull-up resistors to SADD1 and/or SADD2 for proper initialization. ‡‡3-stated if RSTB = 0 and INT0 = 1. Output = CKI (1x) or CKI/2 (2x) if RSTB = 0 and INT0 = 0. §§DSP1628/29 only. DRAFT COPY Lucent Technologies Inc. 15-3...
Page 355 ††For SIO multiprocessor applications, add external pull-up resistors to SADD1 and/or SADD2 for proper initialization. ‡‡3-stated if RSTB = 0 and INT0 = 1. Output = CKI (1x) or CKI/2 (2x) if RSTB = 0 and INT0 = 0. §§DSP1628/29 only. DRAFT COPY 15-4 Lucent Technologies Inc.
Page 356: Signal Descriptions
If the PLL is selected on the DSP1627/28/29, the CKO frequency equals the input CKI frequency regardless of how the PLL is programmed. A logic 0. A logic 1. DRAFT COPY Lucent Technologies Inc. 15-5...
Page 357: External Memory Interface
External Memory Address Bus: Output only. This 16-bit bus supplies the address for read or write operations to the external memory or I/O. DB[15:0] External Memory Data Bus: This 16-bit bidirectional data bus is used for read or write operations to the external memory or I/O. 1.DSP1617 only. DRAFT COPY 15-6 Lucent Technologies Inc.
Page 358: Serial Interface #1
The serial interface pins implement a full-featured synchronous/asynchronous serial I/O channel. In addition, sev- eral pins offer a glueless TDM interface for multiprocessing communication applications (see Figure 7-11). 1.DSEL not available in the DSP1627/28/29. DRAFT COPY Lucent Technologies Inc. 15-7...
Page 359 Output Buffer Empty: Positive assertion. OBE1 is asserted when the output buffer (sdx(OUT)) is emptied (moved to the output shift register for transmission). It is cleared with a write to the buffer, e.g., sdx = a0. OBE1 is also set by asserting RSTB. DRAFT COPY 15-8 Lucent Technologies Inc.
Page 360: Pio/Phif Or Serial Interface #2 And Control I/O Interface
PB[3:0] are pin-multiplexed with SIO2 functionality, and PB[7:4] are pin-multiplexed with BIO unit pins IOBIT[3:0] (see Section 8.4.1). PSEL[2:0] (DSP1617 Only) Peripheral Select 2—0 (see Table 8-5): If the PIO configuration for both input and output are in active mode, this 3-bit field is an output.
Page 361 On the DSP1617 only, the PIO also supports an active mode, where PIDS is an output and is asserted by the DSP1617. If PIDS is low in active mode, data can be placed on the PB bus by an external device. In both active and passive modes, the DSP1617 reads the contents of the PB bus on the rising edge (low-to-high transition) of PIDS.
Page 362: Control I/O Interface
In addition, internal circuitry allows the device to be controlled through the JTAG port to provide on-chip in-circuit emulation. Lucent Technologies provides hardware and soft- ware tools to interface to the on-chip HDS via the JTAG port.
Page 363: Resetting Dsp161X And Dsp162X Devices
RSTB pin or a reset by using the Hardware Development System. 1.The JTAG Test Access Port fully conforms to the standards defined in IEEE P1149.1. 2.See Section 11.3.2, The TAP Controller for more information. DRAFT COPY 15-12 Lucent Technologies Inc.
Page 364: Rstb Pin Reset
RSTB deassertion is specified by t126 to ensure proper CKI—CKO phase relationship after reset. 1.An internal device signal not directly visible to the user. 2.See Section 3.1.3, Register Reset Values or the data sheet. DRAFT COPY Lucent Technologies Inc. 15-13...
Page 365: Mask-Programmable Options
April 1998 15.4 Mask-Programmable Options The DSP1617/18/27/28/29 contains an internal ROM that is mask-programmable. The selection of several pro- grammable features is made when a custom ROM is encoded. These features select the input clock options and hardware emulation or ROM security option as summarized in Table 15-3.
Page 366: Additional Electrical Characteristics And Requirements For Crystal
15.4.2 ROM Security Options (DSP1617/18/27/28/29 Only) (continued) If ROM security is desired with the DSP1617/18/27/28/29, the HDS cannot be used. To provide testing of the inter- nal ROM contents, a cyclic redundancy check (CRC) program is called by and linked to the user's source code.
Page 367 Appendix A Instruction Encoding...
Page 368 APPENDIX A. INSTRUCTION ENCODING CONTENTS A Instruction Encoding............................ A-1 Instruction Encoding Formats ......................A-1 Field Descriptions ..........................A-4...
Page 369: A Instruction Encoding
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR April 1998 A Instruction Encoding This section defines the hardware-level encoding of the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 device instructions. A.1 Instruction Encoding Formats Multiply/ALU Instructions Format 1: Multiply/ALU Read/Write Group 15—11 8—5...
Page 370 15—12 11—0 Field Format 5: Branch Indirect Group 15—11 10—8 7—0 Field reserved Format 6: Conditional Branch Qualifier/Software Interrupt (icall) Note: A branch instruction immediately follows, except for a software interrupt (icall). 15—11 9—6 5—0 Field reserved Lucent Technologies Inc.
Page 371: Instruction Encoding Formats
Field Immediate Operand (IM16) Format 9: Short Immediate Group 15—11 10—9 8—0 Field Short Immediate Operand (IM9) Format 9a: Direct Addressing 15—11 9—6 4—0 Field DR[3:0] OFFSET Cache Instructions Format 10: do—redo 15—11 10—7 6—0 Field Lucent Technologies Inc.
Page 372: Table A-2. B Field
= insert(aS, IM16) 1010 10nn aD = insert(aS, arM) 0111 0000 aD = aS : aa0 0111 0001 aD = aS : aa1 Note: nn encodes the auxiliary register to be used (00—ar0, 01—ar1, 10—ar2, or 11—ar3). Lucent Technologies Inc.
Page 373: Field Descriptions
11100 lock/ebusy 0111 ‡ 01101 c1lt 11101 ebusy 1000 01110 true 11110 Reserved 1001 01111 false 11111 Reserved 1010 † In DSP1627/28/29 only, lock. In DSP1618 only, ebusy. 1011 ‡ DSP1628 only. 1100 1101 1110 1111 Lucent Technologies Inc.
Page 374: Table A-7. F1 Field
= y 1100 aD = y 1101 aD = aS + y 1101 aD = aS + 1 1110 aD = aS & y 1110 aD = aS 1111 aD = aS – y 1111 aD = –aS Lucent Technologies Inc.
Page 375: Table A-9. F3 Field
K Field used. Number of times the N instructions in cache are to be executed. Zero specifies use of value in cloop register. N Field Number of instructions to be loaded into the cache. Zero implies redo operation. Lucent Technologies Inc.
Page 376: Table A-11. R Field For Dsp1617
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual Instruction Encoding April 1998 A.2 Field Descriptions (continued) R Field R field specifies the register for data move instructions. Table A-11. R Field for DSP1617 Table A-12. R Field for DSP1611/18/27/28/29 Register Register Register Register 000000 100000...
Page 377: Table A-13. S Field
Y = a0[l] 11101 Z : y x = X † 11110 bit5 = 0, F4 ALU (BMU) 11110 bit5 = 1, direct addressing 11111 y = Y x = X † These instructions are not available in DSP16A. Lucent Technologies Inc.
Page 378: Table A-17. X Field
Table A-18. Y Field 1101 *r3pz Operation 1110 *r3m2 0000 1111 *r3jk 0001 *r0++ 0010 *r0–– 0011 *r0++j 0100 0101 *r1++ 0110 *r1–– 0111 *r1++j 1000 1001 *r2++ 1010 *r2–– 1011 *r2++j 1100 1101 *r3++ 1110 *r3–– 1111 *r3++j A-10 Lucent Technologies Inc.
Page 379 Appendix B Instruction Set Summary...
Page 380 APPENDIX B. INSTRUCTION SET SUMMARY CONTENTS B Instruction Set Summary..........................B-1 goto JA ............................... B-1 goto B ................................. B-2 if CON goto/call/return..........................B-3 call JA................................. B-4 icall ................................B-5 do K {................................B-6 redo K................................. B-7 R = IM16 ..............................B-8 SR = IM9 ..............................
Page 381 aD = extractz (aS, IM16) .......................... B-52 aD = insert (aS, arM)..........................B-53 aD = insert (aS, IM16) ..........................B-54 aD = aS : aaT ............................B-55...
Page 382: B Instruction Set Summary
Information Manual Instruction Set Summary April 1998 B Instruction Set Summary This section explains in detail the instruction set for the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629. Refer to Appendix A for instruction set formats and field encodings. goto JA (branch direct) (PC) ←...
Page 383: Goto B
† For this instruction, note that the current PC is also saved in the pr register before the jump. 10—8 Field Words: 1 Cycles: 2 Group: Control Addressing: Register Flags affected: None Interruptible: No Cacheable: No Format: 5 DRAFT COPY Lucent Technologies Inc.
Page 384: If Con Goto/Call/Return
Note: ireturn and icall are the only control instructions that cannot be conditionally executed. 4—0 Field word 1 word 2 CONTROL OPCODE Words: 1 (not including the control statement) Cycles: 3 (including the branch/call/return) Group: Control Addressing: None Flags affected: None Interruptible: No Cacheable: No Format: 6 DRAFT COPY Lucent Technologies Inc.
Page 385: Call Ja
4 Kword page. If the call is placed there, the program counter will have incremented to the next page and the jump will be to the next page rather than to the desired current page. Words: 1 Cycles: 2 Group: Control Addressing: Immediate Flags affected: None Interruptible: No Cacheable: No Format: 4 DRAFT COPY Lucent Technologies Inc.
Page 386: Icall
Note that icall vectors to memory address two. The interrupt acknowledge pin (IACK) is set just as it would be by an external interrupt. Field Words: 1 Cycles: 3 Group: Control Addressing: None Flags affected: None Interruptible: No Cacheable: No Format: 6 DRAFT COPY Lucent Technologies Inc.
Page 387: Do K
The instructions remain in the cache memory and may be re-executed using the redo instruction without the need to reload the cache. 10—7 6—0 Field Words: 1 Cycles: 1 Group: Cache Addressing: Immediate Flags affected: None Interruptible: No Cacheable: No Format: 10 DRAFT COPY Lucent Technologies Inc.
Page 388: Redo K
Thereafter, instructions fetched from X-space require their normal out-of-cache time to execute. 6—0 Field Words: 1 Cycles: 2 Group: Cache Addressing: Immediate Flags affected: None Interruptible: No Cacheable: No Format: 10 DRAFT COPY Lucent Technologies Inc.
Page 389: R = Im16
††Writing the psw also writes the a0 and a1 guard bits. Note: If an R field is defined differently for any one of the devices, the register replacement is shown for all six in the following format: DSP1611-register/DSP1617-register/DSP1618&28-register/DSP1627&29-register. DRAFT COPY Lucent Technologies Inc.
Page 390 R = IM16 (16-bit [long] immediate load) (continued) 9—4 Field word 1 word 2 Immediate Value (IM16) Words: 2 Cycles: 2 Group: Data Move Addressing: Immediate Flags affected: None Interruptible: Yes Cacheable: No Format: 8 DRAFT COPY Lucent Technologies Inc.
Page 391: Sr = Im9
(if the value of IM9 is greater than 9 bits, it is trun- cated to 9 bits). For example, set r3 = var1 forces a short immediate encoding. DRAFT COPY Lucent Technologies Inc. B-10...
Page 392: R = As[L
The value of X can be zero to select aS or one to select aSl. Note: Writing the psw also writes the a0 and a1 guard bits. 9—4 Field Words: 1 Cycles: 2 Group: Data Move Addressing: Register Flags affected: None Interruptible: Yes Cacheable: Yes Format: 7 DRAFT COPY B-11 Lucent Technologies Inc.
Page 393: At[L] = R
If a two-cycle data move is desired, the optional mnemonic move may be used. Only the upper 16 bits of y are transferred and no flags are affected. For example: move a0 = y DRAFT COPY Lucent Technologies Inc. B-12...
Page 394: R = Y
*rM– – followed by R = *rM and is used for stack operations. The pointer register rM is decremented, and data is written from the new memory location to the register R. The decrement instruction is not interruptible. DRAFT COPY B-13 Lucent Technologies Inc.
Page 395: Y = R
Register sources c0, c1, and c2 are less than 16 bits and are sign-extended. Register source auc is less than 16 bits and is zero-extended. 9—4 3—0 Field Words: 1 Cycles: 2 Group: Data Move Addressing: Register, Register Indirect Flags affected: None Interruptible: Yes Cacheable: Yes Format: 7 DRAFT COPY Lucent Technologies Inc. B-14...
Page 396: Z : R
Interruptible: Yes Cacheable: Yes Format: 7 Note: R and rM must not be the same register (e.g., r2pz : r2). The eight logical PIO registers pdx0 through pdx7 cannot be used in compound data moves. DRAFT COPY B-15 Lucent Technologies Inc.
Page 397: Dr = *(Offset
31. If clearing of a0l, a1l, or yl is enabled in the auc register, writes to a0, a1, or y will cause bits 15—0 of that register to be cleared. 9—6 4—0 Field OFFSET Words: 1 Cycles: 2 Group: Data Move Addressing: Indirect, Register, Direct Flags affected: None Interruptible: Yes Cacheable: Yes Format: 9a DRAFT COPY Lucent Technologies Inc. B-16...
Page 398: (Offset) = Dr
0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 9—6 4—0 Field OFFSET Words: 1 Cycles: 2 Group: Data Move Addressing: Indirect, Register, Direct Flags affected: None Interruptible: Yes Cacheable: Yes Format: 9a DRAFT COPY B-17 Lucent Technologies Inc.
Page 399: If Con F2
Note: The D and S fields are used to specify aD and aS. Words: 1 Cycles: 1 Group: Special Function Addressing: Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 3 DRAFT COPY Lucent Technologies Inc. B-18...
Page 400: Ifc Con F2
Note: The D and S fields are used to specify aD and aS. Words: 1 Cycles: 1 Group: Special Function Addressing: Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 3 DRAFT COPY B-19 Lucent Technologies Inc.
Page 401: F1 Y
† Code 11, in this case, means add the current value of the j regis- ter to rM after accessing *rM. Note: When code 10 (postdecrement) is specified, this instruction is noninterruptible. It is used to implement the pop(*rM) instruction. DRAFT COPY Lucent Technologies Inc. B-20...
Page 402 (multiply/ALU operation with postmodification of pointer register) (continued) 8—5 3—0 Field Words: 1 Cycles: 1 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes (except for postdecrement) Cacheable: Yes Format: 1 DRAFT COPY B-21 Lucent Technologies Inc.
Page 403: F1 Y = A0[L
Symbol no action postincrement *rM++ postdecrement *rM– – † postincrement by (j) *rM++j † Code 11, in this case, means add the current value of the j regis- ter to rM after accessing *rM. DRAFT COPY Lucent Technologies Inc. B-22...
Page 404: F1 Y = A0[L
8—5 3—0 Field Words: 1 Cycles: 2 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-23 Lucent Technologies Inc.
Page 405: F1 X = Y
2. Access the Y-space location pointed to by rM, and write this value into the x register. rM is specified by the most significant bits of the Y field: 00 - r0 01 - r1 10 - r2 11 - r3 DRAFT COPY Lucent Technologies Inc. B-24...
Page 406: F1 X = Y
† Code 11, in this case, means add the current value of the j regis- ter to rM after accessing *rM. 8—5 3—0 Field Words: 1 Cycles: 1 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-25 Lucent Technologies Inc.
Page 407: F1 Y[L] = Y
Y field: 00 - r0 01 - r1 10 - r2 11 - r3 The X field selects y or yl: X = 0 → yl X = 1 → y DRAFT COPY Lucent Technologies Inc. B-26...
Page 408: F1 Y[L] = Y
† Code 11, in this case, means add the current value of the j regis- ter to rM after accessing *rM. 8—5 3—0 Field Words: 1 Cycles: 1 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-27 Lucent Technologies Inc.
Page 409: F1 Y = Y X = *Pt++[I
2. Access the Y-space location pointed to by rM, and write this value into the y register. rM is specified by the two most significant bits of the Y field: 00 - r0 01 - r1 10 - r2 11 - r3 DRAFT COPY Lucent Technologies Inc. B-28...
Page 410: F1 Y = Y X = *Pt++[I
X = 1 → *pt++i 8—5 3—0 Field Words: 1 Cycles: 2 (1 cycle if in cache) Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-29 Lucent Technologies Inc.
Page 411: F1 Y = A0 X = *Pt++[I
3. Access the X-space location pointed to by pt, and write this value into the x register. Either internal or exter- nal X-space may be accessed depending on the address and the state of the EXM pin. DRAFT COPY Lucent Technologies Inc. B-30...
Page 412: F1 Y = A0 X = *Pt++[I
X = 1 → *pt++i 8—5 Field Words: 1 Cycles: 2 (1 cycle if in cache) Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-31 Lucent Technologies Inc.
Page 413: F1 At[L] = Y
Y field: 00 - r0 01 - r1 10 - r2 11 - r3 The X field selects aT or aTl: X = 0 → aTl X = 1 → aT DRAFT COPY Lucent Technologies Inc. B-32...
Page 414: F1 At[L] = Y
† Code 11, in this case, means add the current value of the j regis- ter to rM after accessing *rM. 8—5 3—0 Field Words: 1 Cycles: 1 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-33 Lucent Technologies Inc.
Page 415: F1 Y = Y[L
Y field: 00 - r0 01 - r1 10 - r2 11 - r3 The X field selects y or yl: X = 0 → y X = 1 → y DRAFT COPY Lucent Technologies Inc. B-34...
Page 416: F1 Y = Y[L
† Code 11, in this case, means add the current value of the j regis- ter to rM after accessing *rM. 8—5 3—0 Field Words: 1 Cycles: 2 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 1 DRAFT COPY B-35 Lucent Technologies Inc.
Page 417: F1 Z : Y[L
00 - r0 01 - r1 10 - r2 11 - r3 4. Postmodify the value of rM using the first action described by the two least significant bits of the Z field described below. DRAFT COPY Lucent Technologies Inc. B-36...
Page 418: F1 Z : Y[L
† Code 11, in this case, means add the current value of the j or k register to rM after accessing *rM. 8—5 3—0 Field Words: 1 Cycles: 2 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 2 DRAFT COPY B-37 Lucent Technologies Inc.
Page 419: F1 Z : At[L
00 - r0 01 - r1 10 - r2 11 - r3 4. Postmodify the value of rM using the first action described by the two least significant bits of the Z field described below. DRAFT COPY Lucent Technologies Inc. B-38...
Page 420: F1 Z : At[L
† Code 11, in this case, means add the current value of the j or k register to rM after accessing *rM. 8—5 3—0 Field Words: 1 Cycles: 2 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 2a DRAFT COPY B-39 Lucent Technologies Inc.
Page 421: F1 Z : Y X = *Pt++[I
Section 3.3, Arithmetic and Precision, for the options available when shifting the output of the p register into aS in the above operations.) 2. Save the y register into an internal temporary location (temp). DRAFT COPY Lucent Technologies Inc. B-40...
Page 422: F1 Z : Y X = *Pt++[I
X = 0 → *pt++ X = 1 → *pt++i 8—5 3—0 Field Words: 1 Cycles: 2 Group: Multiply/ALU Addressing: Register Indirect, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 2a DRAFT COPY B-41 Lucent Technologies Inc.
Page 423: Ad = As Op At
= aS & aT 1111 aD = aS – aT others Reserved 8—5 Field Words: 1 Cycles: 1 Group: ALU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: Yes Format: 3a DRAFT COPY Lucent Technologies Inc. B-42...
Page 424: Ad = As Op P
Note: The instructions aD = aS + p and aD = aS – p are identical in function to the equivalent F1 operations. By default, the assembler will produce the F1 encodings for these instructions. To force the (F3) encoding, the optional mnemonic f3 may be used, as in: f3 a0 = a1 – p DRAFT COPY B-43 Lucent Technologies Inc.
Page 425: Ad = As Op Im16
Note: To avoid confusion in understanding the operation of the instruction, the h is not optional in the <h, l> encoding. The X field selects aS or aSl: X = 0 → aSl X = 1 → aS DRAFT COPY Lucent Technologies Inc. B-44...
Page 426 = aS<h,l > – IM16 others Reserved 8—5 Field word1 word2 Immediate Value (IM16) Words: 2 Cycles: 2 Group: ALU Addressing: Immediate, Register Flags affected: LMI, LEQ, LLV, LMV Interruptible: Yes Cacheable: No Format: 3a DRAFT COPY B-45 Lucent Technologies Inc.
Page 427: Ad = A Shift As
01 - >>> 10 - << 11 - <<< 4—3 Field SHIFT Words: 1 Cycles: 2 Group: BMU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: Yes Format: 3b DRAFT COPY Lucent Technologies Inc. B-46...
Page 428: Ad = As Shift Arm
10 - ar2 11 - ar3 4—3 1—0 Field SHIFT Words: 1 Cycles: 1 Group: BMU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: Yes Format: 3b DRAFT COPY B-47 Lucent Technologies Inc.
Page 429: Ad = As Shift Im16
Field word 1 SHIFT word 2 Immediate Value (IM16) Words: 2 Cycles: 2 Group: BMU Addressing: Immediate, Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: No Format: 3b DRAFT COPY Lucent Technologies Inc. B-48...
Page 430: Ad = Exp (As
Operations) are set based on the value written into aD. Field Words: 1 Cycles: 1 Group: BMU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: Yes Format: 3b DRAFT COPY B-49 Lucent Technologies Inc.
Page 431: Ad = Norm (As, Arm
01 - ar1 10 - ar2 11 - ar3 1—0 Field Words: 1 Cycles: 1 Group: BMU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: Yes Format: 3b DRAFT COPY Lucent Technologies Inc. B-50...
Page 432: Ad = Extracts (As, Arm
01 - ar1 10 - ar2 11 - ar3 1—0 Field Words: 1 Cycles: 1 Group: BMU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: Yes Format: 3b DRAFT COPY B-51 Lucent Technologies Inc.
Page 433: Ad = Extracts (As, Im16
X = 1 Field word1 word2 Immediate Value (IM16) Words: 2 Cycles: 2 Group: BMU Addressing: Immediate, Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: No Format: 3b DRAFT COPY Lucent Technologies Inc. B-52...
Page 434: Ad = Insert (As, Arm
01 - ar1 10 - ar2 11 - ar3 1—0 Field Words: 1 Cycles: 2 Group: BMU Addressing: Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: Yes Format: 3b DRAFT COPY B-53 Lucent Technologies Inc.
Page 435: Ad = Insert (As, Im16
Flags are set based on the value written into aD. The LLV flag is set if WIDTH = 0 or if (WIDTH + OFFSET) > 36. Field word1 word2 Immediate Value (IM16) Words: 2 Cycles: 2 Group: BMU Addressing: Immediate, Register Flags affected: LMI, LEQ, LLV, LMV, ODDP, EVENP, MNS1, NMNS1 Interruptible: Yes Cacheable: No Format: 3b DRAFT COPY Lucent Technologies Inc. B-54...
Page 436: Ad = As : Aat
aD = aS : aaT (swap accumulator with alternate accumulator) temp ← (aS); then (aD) ← (aaT); then (aaT) ← temp The contents of alternate accumulator aaT are replaced with the value in aS. The contents of aD are replaced with the old value in aaT.
Page 437 Index...
Page 438 (see instructions, conditional) control block 5-19 LPIDS 8-10 counter PIBF 8-10 conditional mnemonics POBE 8-10 counters (see register, c0; register, c1; and register, c2) processor data address bus (see YAB) data addressing unit (see YAAU) Lucent Technologies Inc.
Page 439 4-11, 4-14—4-15, 5-18 loops conditional and counters 5-4—5-6 nested control 4-11, 4-12, 4-13 using counters for data move 4-11, 4-15—4-18 multiply/ALU 4-11 special function 4-11, 4-19—4-21 interrupt MASK 10-2 EMUXBOTH 6-27 memory EOVF 3-29 addressing 3-8, Lucent Technologies Inc.
Page 440 ALIGN field 3-21, CLR field 3-21, 5-2, offset 14-18 RAND field 3-22, operation SAT field 3-21, interrupt 3-32—3-38 X=Y= field 3-21, 4-24, single-cycle squaring 3-21, 4-24 5-4—5-6 operations 5-4—5-6 concurrent 5-4—5-6 overflow cbit 10-1, 10-2, 10-4, 10-5 Lucent Technologies Inc.
Page 441 OCK field 7-10 PSOBEF field 9-10 OLD field 7-10 PSTRB field OLEN field 7-6, 7-8, 7-10 PSTROBE field sioc2 7-27 pi 2-18, 5-7, 5-11, 5-12 DODLY field pioc 8-1, 8-2, 8-15—8-16 srta 7-1, 7-21 IBF field 8-20 14-14 Lucent Technologies Inc.
Page 442 15-11 logical right (>>>) 13-2 15-11 signal 15-11 AB 6-2, 15-6 15-11 CKI2 15-5 TRAP 15-6 CKO 6-2, 15-5 TRST 15-11 DB 6-2, 15-6 15-6 7-12 15-8 input section 7-4—7-5 7-12 loopback 7-11 15-8 multiprocessor mode 7-15—7-25 Lucent Technologies Inc.
Page 443 X addressing arithmetic unit (see XAAU) XAAU 2-1, 2-2, 2-18, 3-8, 3-10, 5-11—5-12 XAB 2-1, 2-2, 3-10, 5-11 XDB 3-10, Y addressing arithmetic unit (see YAAU) YAAU 2-1, 2-2, 2-17, 3-8, 5-13 YAB 2-1, 3-8, 5-13 YDB 2-1, Lucent Technologies Inc.

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Dsp1629 Dsp1618 Dsp1611 Dsp1627 Dsp1628

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Software Architecture

Chapter 4 Instruction Set

Chapter 5 Core Architecture

Chapter 6 External Memory Interface

Chapter 7 Serial I\/O

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