The Sample Instruction; The Bypass Instruction; The Idcode Instruction - Lucent Technologies DSP1617 Information Manual

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11.4 The JTAG Instruction Set
(continued)
11.4.2 The INTEST Instruction (continued)
The only feature distinguishing the INTEST instruction from the EXTEST instruction is all bidirectional cells are
configured as inputs during INTEST to prevent any contention on bidirectional buses on the board while individual
components are being tested. Any low-speed testing of the device, done by scanning input vectors through the
JBSR, should be performed during the INTEST instruction. In this case, the test results are captured by the O-type
cells of the JBSR and can be shifted out for verification.

11.4.3 The SAMPLE Instruction

The SAMPLE instruction is required by the standard. It connects the boundary-scan register JBSR between TDI
and TDO and configures it in the sample mode. Unlike the INTEST and EXTEST instructions, the SAMPLE
instruction does not interfere with the normal functioning of the device and provides a passive function monitoring
the activities on the device pins. This is achieved by setting the MODE signal to zero during the SAMPLE instruc-
tion that selects the normal flow of data across the JBSR cells (see Figure 11-5 through Figure 11-8). Because the
capture function of the boundary-scan cells is not affected by the MODE signal whether in a test mode or not, the
values of device signals on the input pins or destined for the output pins are always captured in the corresponding
register cells of the JBSR.
With the SAMPLE instruction present in the JIR, a snapshot of the normal activity of the device on its boundary can
be obtained in the capture-DR state and shifted out for diagnostic purposes. This snapshot can also be updated
into the boundary-scan register cells through the TAP Controller transitions (capture-DR, exit1-DR, and update-DR)
while the SAMPLE instruction loads a safe pattern into the output stage of JBSR. This safe pattern can appear on
the I/O pins in a later boundary-scan test instruction such as INTEST or EXTEST where the boundary of the device
needs to be in a known state during the corresponding test operation. System maintenance and support functions,
as well as functional test diagnosis of boards and systems, can also be achieved based on the SAMPLE mode of
the boundary-scan register.

11.4.4 The BYPASS Instruction

The instruction code 0xF corresponds to the BYPASS instruction in the DSP1611/17/18/27/28/29 JTAG design.
Instruction code 0xF corresponds to the all ones instruction (1111) as required by the standard to select the
BYPASS instruction.
The BYPASS instruction selects the 1-bit long bypass register (JBPR) that is used to bypass the boundary-scan
register if the device does not take part in a board test. As mentioned in Section 11.3.5, The Bypass Regis-
ter—JBPR, JBPR loads a zero into the shift-register stage in the capture-DR state. Because JBPR does not con-
tain an output stage, no value is loaded into the bypass register in the update-DR state.

11.4.5 The IDCODE Instruction

The IDCODE instruction connects the device identification register (JIDR) across the TDI-TDO path. A DR-scan
cycle while the IDCODE instruction is present can be used to shift the 32-bit hardwired device identification code
(see Section 11.3.6, The Device Identification Register—JIDR) out of the TDO pin. This instruction is used to iden-
tify the device by its manufacturer, part number, and version number codes. Similar to the bypass register, JIDR
does not contain a parallel output stage and no value can be loaded in the update-DR state. The instruction regis-
ter is initialized to hold the IDCODE value (i.e., 0xE) when entering the test-logic-reset state (e.g., at powerup) as
required by the standard.
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