Intel Mode, 16-Bit Read; Figure 9-2. Intel Mode, 16-Bit Read - Lucent Technologies DSP1617 Information Manual

Information Manual
April 1998
9.1 PHIF Operation

9.1.1 Intel Mode, 16-Bit Read

The external device drives PCSN, PODS, and PBSEL. The DSP places data on PB for the external device to read.
In the Intel mode, PIDS is the input data strobe and PODS is the output data strobe with respect to the DSP.
Initially, PB is 3-stated. Valid data is placed on PB if both PCSN (chip select) and PODS (output data strobe) are
low. The timing of this action is initiated by whichever of the two goes low last. PBSEL (byte-select) is low, so the
low byte from the pdx0(OUT) register is placed on PB. If PODS is driven high by the external device, the data is
latched externally and the DSP can again 3-state the PB. The timing of this action is controlled by PODS or PCSN,
whichever goes high first. PBSEL can now be driven high to select the high byte of pdx0(OUT). The sense of
PBSEL can be reversed by programming the phifc register. The default state is shown here. The cycle is com-
pleted by another strobe from PCSN and PODS. After the high byte is latched into the external device on the rising
edge of PODS, the POBE interrupt is generated and the POBE output pin goes high.
PCSN
(CHIP SELECT)
PODS, FROM
EXTERNAL DEVICE
†
PBSEL
PB, FROM DSP
†
POBE
† The logic levels of these pins can be inverted by programming the phifc register.
Lucent Technologies Inc.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
(continued)
LOW BYTE READ

Figure 9-2. Intel Mode, 16-Bit Read

DRAFT COPY
HIGH BYTE READ
5-4495
9-3