Chapter 22 Reset Function - NEC 78K0 Series User Manual

The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H when the reset signal is generated.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection, and each item of hardware is set to the status shown in Tables 22-1 and 22-2. Each pin is
high impedance during reset signal generation or during the oscillation stabilization time just after a reset release,
except for P130, which is low-level output.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 22-2 to 22-4) after reset processing. Reset by POC and LVI circuit
power supply detection is automatically released when V
execution starts using the internal high-speed oscillation clock (see CHAPTER 23 POWER-ON-CLEAR CIRCUIT
and CHAPTER 24 LOW-VOLTAGE DETECTOR) after reset processing.
Cautions 1. For an external reset, input a low level for 10
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input and external
subsystem clock input become invalid.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance, except for P130, which is set to low-
level output.

CHAPTER 22 RESET FUNCTION

≥ V
DD
Preliminary User's Manual U17260EJ3V1UD
≥ V
or V after the reset, and program
POC DD LVI
µ
s or more to the RESET pin.
521