NEC 78K0 Series User Manual page 641

Page
pp. 467 to 469 Addition of description when (i) When WTIM0 = 0 to the following items in 17.5.17 (6) Operation when
arbitration loss occurs (no communication after arbitration loss)
(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart
condition
(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
pp. 471 to 476 Modification of Figure 17-27 Example of Master to Slave Communication (When 9-Clock Wait Is
Selected for Both Master and Slave) and Figure 17-28 Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave)
CHAPTER 18 MULTIPLIER/DIVIDER (
Modification of Figure 18-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H)
p. 485
CHAPTER 21 STANDBY FUNCTION
p. 508 Modification of Caution 3 in 21.1.1 Standby function
p. 510 Modification of description in 21.1.2 (2) Oscillation stabilization time select register (OSTS)
pp. 512, 513 Addition of clock output and buzzer output to items in and addition of Note to Table 21-1 Operating
Statuses in HALT Mode
p. 515 Modification of Figure 21-4 HALT Mode Release by Reset
p. 517 Addition of clock output and buzzer output to items in and addition of Note to Table 21-3 Operating
Statuses in STOP Mode
p. 518 Modification of Figure 21-5 Operation Timing When STOP Mode Is Released
p. 520 Modification of Figure 21-7 STOP Mode Release by Reset
CHAPTER 22 RESET FUNCTION
p. 523 Modification of Figure 22-2 Timing of Reset by RESET Input
p. 523 Modification of Figure 22-3 Timing of Reset Due to Watchdog Timer Overflow
p. 524 Modification of Figure 22-4 Timing of Reset in STOP Mode by RESET Input
p. 525 Addition of clock output and buzzer output to items in Table 22-1 Operation Statuses During Reset Period
p. 528 Modification of table in Note of Table 22-2 Hardware Statuses After Reset Acknowledgment (3/3)
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
p. 530 Addition of description of 2.7 V/1.59 V POC mode to 23.1 Functions of Power-on-Clear Circuit
p. 531 Modification of 23.3 Operation of Power-on-Clear Circuit
p. 534 Modification of Figure 23-3 Example of Software Processing After Reset Release (1/2)
CHAPTER 24 LOW-VOLTAGE DETECTOR
p. 536 Modification of Figure 24-1 Block Diagram of Low-Voltage Detector
p. 539 Modification of Figure 24-3 Format of Low-Voltage Detection Level Selection Register (LVIS)
p. 543 Addition of (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) to Figure 24-5 Timing of Low-
Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V
pp. 547, 548 Modification of (1) In 1.59 V POC mode (option byte: POCMODE = 0) in and addition of (2) In 2.7 V/1.59 V
POC mode (option byte: POCMODE = 1) to Figure 24-7 Timing of Low-Voltage Detector Interrupt
Signal Generation (Detects Level of Supply Voltage (V
p. 550 Modification of Figure 24-8 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level
of Input Voltage from External Input Pin (EXLVI))
p. 552 Modification of Figure 24-9 Example of Software Processing After Reset Release (1/2)
APPENDIX D REVISION HISTORY
Description
µ
PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY)
Preliminary User's Manual U17260EJ3V1UD
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(6/7)
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