NEC 78K0 Series User Manual page 216

(3) Free-running timer mode operation
(CR00n: capture register, CR01n: capture register)
Count clock
Edge
TI00n pin
detection
Edge
TI01n pin
detection
Remarks 1. If both CR00n and CR01n are used as capture registers in the free-running timer mode, the output
level of the TO0n pin is not inverted.
However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1)
of 16-bit timer mode control register 0n (TMC0n) is set to 1.
2. n = 0:
n = 0, 1:
216
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-41. Block Diagram of Free-Running Timer Mode
(CR00n: Capture Register, CR01n: Capture Register)
Operable bits
TMC0n3, TMC0n2
Capture signal
Capture
signal
µ
PD78F0531, 78F0532, 78F0533
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Preliminary User's Manual U17260EJ3V1UD
Timer counter
(TM0n)
Capture register
(CR01n)
Capture register
(CR00n)
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)