NEC 78K0 Series User Manual page 121

5.2.9 Port 12
Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register 12 (PU12).
This port can also be used as pins for external interrupt request input, potential input for external low-voltage
detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input
for main system clock, and external clock input for subsystem clock.
Reset signal generation sets port 12 to input mode.
Figures 5-22 and 5-23 show block diagrams of port 12.
Caution When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or
subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or
subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock
input mode must be set by using the clock operation mode select register (OSCCTL) (for details,
see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for
subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port
pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary.
Remark The X1 and X2 pins of the
OCD0B) when the on-chip debug function is used. For details, see CHAPTER 27 ON-CHIP DEBUG
µ
FUNCTION (
WR
PU
RD
WR
PORT
Output latch
WR
PM
P12: Port register 12
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
µ
PD78F0537D can be used as on-chip debug mode setting pins (OCD0A,
PD78F0537D ONLY).
Figure 5-22. Block Diagram of P120
PU12
PU120
Alternate
function
P12
(P120)
PM12
PM120
Preliminary User's Manual U17260EJ3V1UD
EV
DD
P-ch
P120/INTP0/EXLVI
121