NEC 78K0 Series User Manual page 220

Figure 7-43. Example of Register Settings in Free-Running Timer Mode (2/2)
(d) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1
0/1 0/1
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
When this register is used as a compare register and when its value matches the count value of TM0n, an
interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared.
To use this register as a capture register, select either the TI00n or TI01n pin input as a capture trigger.
When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n.
(g) 16-bit capture/compare register 01n (CR01n)
When this register is used as a compare register and when its value matches the count value of TM0n, an
interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared.
When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the
valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
220
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
ES0n0 3
0/1 0/1 0
Preliminary User's Manual U17260EJ3V1UD
2 PRM0n1 PRM0n0
0 0/1 0/1
Count clock selection
(setting TI00n valid edge is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(setting prohibited when CRC0n1 = 1)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection