Setting Overflow Time Of Watchdog Timer - NEC 78K0 Series User Manual

Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (LSROSC) of the option byte.
In HALT mode
In STOP mode
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
5. The watchdog timer does not stop during self-programming of the flash memory and
EEPROM
overflow time and window size taking this delay into consideration.

11.4.2 Setting overflow time of watchdog timer

Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing "ACH" to WDTE during the window open period before the overflow time.
The following overflow time is set.
WDCS2
0
0
0
0
1
1
1
1
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
2. The watchdog timer does not stop during self-programming of the flash memory and
Remarks 1. f
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2. ( ): f
CHAPTER 11 WATCHDOG TIMER
LSROSC = 0 (Internal Low-Speed
Oscillator Can Be Stopped by Software)
Watchdog timer operation stops.
TM
emulation. During processing, the interrupt acknowledge time is delayed. Set the
Table 11-3. Setting of Overflow Time of Watchdog Timer
WDCS1 WDCS0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
is prohibited.
EEPROM emulation. During processing, the interrupt acknowledge time is delayed.
Set the overflow time and window size taking this delay into consideration.
: Internal low-speed oscillation clock frequency
= 264 kHz (MAX.)
RL
Preliminary User's Manual U17260EJ3V1UD
Watchdog timer operation continues.
Overflow Time of Watchdog Timer
10
2 /f (3.88 ms)
RL
11
2 /f (7.76 ms)
RL
12
2 /f (15.52 ms)
RL
13
2 /f (31.03 ms)
RL
14
2 /f (62.06 ms)
RL
15
2 /f (124.12 ms)
RL
16
2 /f (248.24 ms)
RL
17
2 /f (496.48 ms)
RL
LSROSC = 1 (Internal Low-Speed
Oscillator Cannot Be Stopped)
297