NEC 78K0 Series User Manual page 243

(7) Operation of OVF0n flag
(a) Setting OVF0n flag (1)
The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows.
Select the clear & start mode entered upon a match between TM0n and CR00n.
↓
Set CR00n to FFFFH.
↓
When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
(b) Clearing OVF0n flag
Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted
(before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid.
(8) One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the
TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match
between TM0n and CR00n.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-62. Operation Timing of OVF0n Flag
Count pulse
CR00n FFFFH
TM0n FFFEH FFFFH
OVF0n
INTTM00n
Preliminary User's Manual U17260EJ3V1UD
0000H 0001H
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