NEC 78K0 Series User Manual page 513

HALT Mode Setting
Item
System clock
Main system clock f
RH
f
X
f
EXCLK
Subsystem clock f
XT
f
EXCLKS
f
RL
CPU
Flash memory
RAM
Port (latch)
Note1
16-bit timer/event 00
counter
Note1. 2
01
Note1
8-bit timer/event 50
counter
Note1
51
8-bit timer H0
H1
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface UART0
UART6
Note1
CSI10
Note1, 2
CSI11
Note1
IIC0
Note2
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
µ
2. PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
Remark f : Internal high-speed oscillation clock
RH
f : X1 clock
X
f : External main system clock
EXCLK
f : XT1 clock
XT
f : External subsystem clock
EXCLKS
f : Internal low-speed oscillation clock
RL
CHAPTER 21 STANDBY FUNCTION
Table 21-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
When CPU Is Operating on XT1 Clock (f
Clock supply to the CPU is stopped
Status before HALT mode was set is retained
Operates or stops by external clock input
Operation continues (cannot be stopped)
Operates or stops by external clock input
Status before HALT mode was set is retained
Operation stopped
Operation stopped
Status before HALT mode was set is retained
Status before HALT mode was set is retained
Operable
Operable. Clock supply to watchdog timer stops when "internal low-speed oscillator can be
stopped by software" is set by option byte.
Operable
Operable. However, operation disabled when peripheral hardware clock (f
Operable
Preliminary User's Manual U17260EJ3V1UD
) When CPU Is Operating on External
XT
Subsystem Clock (f
Status before HALT mode was set is retained
Operation continues (cannot be stopped)
)
EXCLKS
) is stopped.
PRS
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