NEC 78K0 Series User Manual page 532

Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
V
LVI
Supply voltage
(V )
DD
Note 1
1.8 V
V = 1.59 V (TYP.)
POC
0.5 V/ms (MAX.)
0 V
Wait for oscillation
accuracy
stabilization
Internal high-speed
oscillation clock (f )
RH
Starting oscillation is
High-speed
specified by software.
system clock (f )
XH
(when X1 oscillation
is selected)
Wait for voltage
stabilization
Operation (3.24 ms (TYP.))
CPU
stops
Reset processing (20 s (TYP.))
Internal reset signal
The operation guaranteed range is 1.8 V ≤ V
Notes 1.
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MAX.) on power application, input a low
level to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7
V/1.59 V POC mode by using an option byte (POCMODE = 1).
3. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
LOW-VOLTAGE DETECTOR).
Remark V : LVI detection voltage
LVI
V : POC detection voltage
POC
532
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
and Low-Voltage Detector (1/2)
Set LVI to be Set LVI to be
used for reset used for interrupt
Note 2
Wait for oscillation
accuracy
stabilization
Reset period
Normal operation
(oscillation
(internal high-speed
stop)
Note 3
oscillation clock)
µ
Reset processing (20 s (TYP.))
Preliminary User's Manual U17260EJ3V1UD
Wait for oscillation
accuracy
stabilization
Starting oscillation is Starting oscillation is
specified by software. specified by software.
Reset period Wait for voltage
Normal operation
(oscillation stabilization
(internal high-speed
stop) (3.24 ms (TYP.))
Note 3
oscillation clock)
µ
Reset processing (20 s (TYP.))
≤ 5.5 V. To make the state at lower than 1.8 V reset
DD
Set LVI to be
used for reset
Normal operation
(internal high-speed
Note 3
oscillation clock)
Operation stops
µ